# Gujarat University 2007 B.E Computer Engineering-Digital Logic

2/867 Candidates Seat No'

GUJARAT UNIVERSITY B. E. Seoi 111 (C.E.) (New) Examination Digital Logic & Design

Thursday 27tb December* 2007) |Time : 3 Hours

Max. Marks : ]00

Instructions : (1) Attempt all questions.

(2) Answer to the two sections must be written in separate answer books,

(3) Assume suitable data if required.

(4) Figures to the right indicate full marks.

SECTION I

1 Answer the following : 18 ( a ) Why NAND and NOR gate are called universal gate?

( b ) Convert the following gray codc to binary :(i) 1111 (ii) 1001.

( c ) Fill in the banks : ( i ) (123), = (.......?.......)_{4} ( ii ) (777), + (12), = (......?......),.

( d ) Perform the substration (3570)_{lo} - (2100)_{10} using 10s complement and 9s complement method.

( e ) Implement expression with NAND logic : X = ABC + DE.

2 ( a ) Obtain the simplified expression using dont care condition ^{c}d\ in ( i ) sum of products : 6

(ii ) product of sums :

F (w. x, y, z) = Z (0, 1, 2. 3, 7, 8, 10) d (w, x, y, z) = (5, 6;, II, 15).

( b ) Express the following functions in a sum of minterms : 4

( i ) F (A, B, C) = (A + BXB + C) ( ) F (X, Y, Z) = (XY + Z) (Y + XZ)

( c ) Simplify the following Boolean function using tabulation method : 6

FI (A, B, C, D) = n_{M} (I, 5, 6, 7, 11, 12, 13, 15)

OR

2 ( a ) Design a minimal circuit to produce an output of 1, when its input is 2421 code represen- 6 ting an even decimal number less than 10.

( b ) Design each of the following circuits than can be built using AOl logic and outputs a I, 10 when;

(i ) A 4-bit hexadecimal input is an odd number from 0 to 9.

( ii) A 4-bit BCD code translated to a number that uses the upper right segment of seven segment display.

( a ) |
Explain briefly the difference between MUX and DEMUX |
3 |

(b) |
Construct Gray to binary code converter. |
8 |

( c ) |
State & prove Demorgans law with suitable examples. |
5 |

OR | ||

(a) |
Design a 4-bit odd parity checker circuit. |
4 |

(b) |
Write short note on : (i) BCD Adder ( ii) Look Ahead Carry generator. |
8 |

( c) |
Using Boolean algebra, prove the following : |
4 |

( i ) AB + X |

SECTION II

4 ( a ) Explain Master slave flipflop through JK flipflop. 8

( b ) Design a sequential circuit with JK flip flop to satisfy following state equation : 8

^{A}(^{t+1})^{=}AB ^{+} ABC+ ACD + Ac p

^{B} + 0 = A^{C +} CD ^{+} A^{b}C

C (t + 1) - A D (t + I) = g

5 |
( a ) |
Implement the following Boolean function with 8 x 1 multiplexer with A, B and D connected |
6 |

to selection lines s | |||

(b) |
Design a counter with the following binary sequence : 0,1, 3, 7, 6,4 and repeat. |
6 | |

Use T flip flops. | |||

(c) |
Explain the working principle of BCD to 7 segment decoder, |
4 | |

OR | |||

5 |
( a) |
Define the following terms : (i ) Fan in { ii) fan-out (iii) Figure of merit |
6 |

(iv ) Propogation delay ( v ) Noise Margin and ( vi) Thresold voltage. | |||

(b) |
Discuss about Ripple counter in detail. |
8 | |

(c) |
What do you mean by interfacing of logic families? What is need of that? |
2 | |

6 |
Write short note on (any three) : |
18 | |

( a ) |
Magnitude comparator | ||

(b) |
Classification of registers | ||

(c) |
ECL & TTL logic families | ||

(d) |
CMOS logic family | ||

(e) |
Static & dynamic RAM. |

f

Attachment: |

Earning: Approval pending. |