Calicut University 2007 B.E Electronics and Instrumentation Engineering FIFTH SEMESTER B.TECH.(ENGINEERING) - COMPUTER ORGANIZATION AND ARCHITECTURE - Question Paper

C32245

FIFTH SEMESTER B.TECH.(ENGINEERING) DEGREE EXAMINATION,JUNE 2007
BM/AI 04 504 – COMPUTER ORGANIZATION AND ARCHITECTURE

Time: 3 hours Maximum Marks: 100 Marks

ans all ques.

Part A

1.

a) What are the steps in executing a complete instruction?

b) Explain the different Bus structures.

c) Explain what is meant by memory hierarchy?

d) Explain the functions of memory management.

e) Explain the different graphic input devices.

f) Explain what is meant by data dependency in a pipeline?

g) Explain the principles in linear pipelining.

h) Explain 2 parallel processing applications.

(8x5 =40 marks)


Part B

2.(a)


I. Explain the methods used for encoding info.(7 marks)

II. Explain the steps in fetching a word from memory and storing a word in memory.(8 marks)

Or

(b) discuss the design of a Hardwired control unit. Also explain its advantages and disadvantages.(15 marks)

3.(a)

I. Compare the speed, size and cost of RAM and Cache memory.(7 marks)

II. Explain the design of a fast adder.(8 marks)

Or

(b)

I. Explain the address translation mechanism in a virtual memory system.(8 marks)

II. Explain signed operand multiplication with help of an example.(7 marks)

4.(a)

I. Explain the principle of operation of any 2 output devices.(10 marks)

II. What do you mean by an instruction queue?(5 marks)

Or

(b)

I. Discuss the factors which help to study the performance of disk access and communication lines.(8 marks)

II. What is meant by Speedup and Throughput of a pipeline?(7 marks)


5.(a)

I. Give an example of a linear pipeline performing 2 functions. Draw their reservation tables.(8 marks)

II. Explain the different parallel computer structures.(7 marks)

Or
(b)

I. What do you mean by interleaved memory organization?(8 marks)

II. What do you mean by instruction and arithmetic pipelines?(7 marks).

Earning:   Approval pending.