Calicut University 2007 B.E Electronics and Instrumentation Engineering SEVENTH SEMESTER B.TECH(ENGINEERING) - DIGITAL MOS CIRCUITS - Question Paper

D 42546

SEVENTH SEMESTER B.TECH. (ENGINEERING) DEGREE EXAMINATION, DECEMBER 2007

AI O4 703-DIGITAL MOS CIRCUITS

Time: 3 Hours
Maximum: 100 Marks

ans all ques..

1.
(a) Draw the schematic of Digital MOSFET model and discuss.

(b) explain about the causes and effects of drain induced barrier lowering.

(c) Draw the schematic of three stage ring oscillator and find the expression for its frequency of oscillation.

(d) Name the models that are used to represent the interconnects and explain about 1 model briefly

(e) With the help of circuit diagram, discuss the operation of Bi-CMOS inverter circuit with active base pull down.

(f) When 2 MOSFETs are connected in parallel how they will behave? What will be the effective width and transconductance?

(g) What is a Domino logic? State the advantages of Domino logic.

(h) What is the use of “Keeper” MOSFET? discuss.

(8x5=40 Marks)

2.
(a) explain in detail the effect of narrow channel on MOS transistor characteristics.

Or

(b) explain in detail about:

(i) Hot electron effects.

(ii) Velocity saturation of charge carriers.

(iii) Channel length modulation.

(3x5=15 Marks)

3.
(a) compute VIL and VIH for CMOS INVERTER.

Or

(b) explain about estimation of interconnect parasitic.

4.
(a) Draw the circuit diagram of COMS NAND gate and discuss its operation. Also derive the expression for its switching threshold voltage.

Or

(b) Design a CMOS full adder using CMOS AOI logic.

5.
(a) Draw the schematic of adiabatic amplifier circuit and discuss its operation, also discuss how this circuit principle can be extended to implement logic functions.

Or

(b) Draw the dynamic CMOS logic (precharge evaluate logic) to realize the function
F=(xyz + pq)' and discuss
(4x15=60 Marks)

Earning:   Approval pending.