Lovely Professional University 2010 B.Tech Computer Science and Engineering Assignment -2 Computer System and Architecture - Question Paper

TBA 2

Course No. CSE 261

Course Title: Computer Organization and Architecture

PART-A

Q1. The adder- subtractor circuit has the subsequent values for input mode M and data inputs A & B.

In every case determine the values of the outputs: S3, S2, S1, S0 and C4

M A B
0 0111 0110
0 1000 1001
1 1100 1000
1 0101 1010
1 0000 0001

Q2. Design a 4 bit combinational circuit incrementer and decrementer using full adders.

Q3. Register A holds the eight bit binary 11011001. Determine the B operand and the logic micro

operation to be performed in order to change the value in A to (a) 01101101 (b) 11111101

Q4. Starting from initial value of R=11011101, determine the sequence of binary values in R after a

logic shift left followed by circular shift right, followed by a logical shift right and a circular

shift

Q5. Fetching and decoding of any instruction takes 3 clock cycles. How?

PART-B

Q6. Draw timing diagram for D3T4: SC ? 0

Q7. How is I bit useful in determining the kind of instruction

Q8. Why is micro programmed control better than hardwired? Identify a few situations when hardwired

is preferred.

Q9. How are data, address and control buses involved in data transfer to and from memory? Consider

a computer system with 16 registers of 32 bit every and RAM of 1GB. compute the size of data bus

and address bus needed for the identical.

Earning:   Approval pending.