Lovely Professional University 2010 B.Tech Computer Science and Engineering Assignment -3 Computer System and Architecture - Question Paper
Course No. CSE 261
Course Title: Computer Organization and Architecture
Note: Students are to attempt all assignment ques. and test may be from similar issues but may be with slightly various logic and various data sets
PART-A
Q1. How are data, address and control buses involved in data transfer to and from memory? Consider a computer system with 16 registers of 32 bit every and RAM of 1GB. compute the size of data bus and address bus needed for the identical.
Q2. A Bus organised CPU has 16 registers with 32 bits in each, a ALU and a destination Decoder.
(a) How many multiplexers are there in the A bus and what is the size of every multiplexer?
(b) How many selection inputs are needed for MUX A and MUX B?
(c) How many inputs and outputs are there in the decoder?
(d) How many inputs and outputs are there in the ALU for data and input output carries?
(e) Formulate the control word for the system assuming that the ALU has 35 operations
Q3. Specify the control word in order to implement the subsequent micro operations
(a) R1?R2+R3
(b) R4?R4
(c) R7?input
Q4. Determine the micro operation that will be executed in the processor when subsequent 14 bit control words are applies
(a) 00101001100101
(b) 00000000000000
Q5. Write a program to evaluate the arithmetic statement
A*[B+C*(D+E)]
F*(G+H)
(a) Using three address instructions
(b) Using two address instructions
(c) Using one address instructions
(d) Using 0 address instructions
PART-B
Q6. An instruction is stored at location 300 with its address field at location 301. The address field has the value 400. A processor register R1 contains 200. Evaluate the effective address if the addressing mode is
(a) direct
(b) immediate
(c) relative
(d) register indirect
(e) index with R1 as index register
(f) register
Q7. Show the contents of E, A, Q and SC during the process of multiplication of 2 binary numbers, 11111 (multiplicand) and 10101(multiplier).
Q8. Perform the identical multiplication using Booth Algorithm
Q9. Show the contents of E, A, Q and SC during the process of division of 2 binary numbers, 10100011 by 1011.
Q10. Show that adding B after A+B+1 restores the original value of A. What should be done with end carry?
Assignment No 3
Course No. CSE 261 Course Title: Computer Organization and Architecture
Note: Students are to attempt all assignment questions and test may be from similar problems but may be with slightly different logic and different data sets
PART-A
Q1. How are data, address and control buses involved in data transfer to and from memory? Consider a computer system with 16 registers of 32 bit each and RAM of 1GB. Calculate the size of data bus and address bus required for the same.
Q2. A Bus organised CPU has 16 registers with 32 bits in each, a ALU and a destination Decoder.
(a) How many multiplexers are there in the A bus and what is the size of each multiplexer?
(b) How many selection inputs are needed for MUX A and MUX B?
(c) How many inputs and outputs are there in the decoder?
(d) How many inputs and outputs are there in the ALU for data and input output carries?
(e) Formulate the control word for the system assuming that the ALU has 35 operations
Q3. Specify the control word in order to implement the following micro operations
(a) R1←R2+R3
(b) R4←R4
(c) R7←input
Q4. Determine the micro operation that will be executed in the processor when following 14 bit control words are applies
(a) 00101001100101
(b) 00000000000000
Q5. Write a program to evaluate the arithmetic statement
A*[B+C*(D+E)]
F*(G+H)
(a) Using 3 address instructions
(b) Using 2 address instructions
(c) Using 1 address instructions
(d) Using 0 address instructions
PART-B
Q6. An instruction is stored at location 300 with its address field at location 301. The address field has the value 400. A processor register R1 contains 200. Evaluate the effective address if the addressing mode is (a) direct (b) immediate (c) relative (d) register indirect (e) index with R1 as index register (f) register
Q7. Show the contents of E, A, Q and SC during the process of multiplication of two binary numbers, 11111 (multiplicand) and 10101(multiplier).
Q8. Perform the same multiplication using Booth Algorithm
Q9. Show the contents of E, A, Q and SC during the process of division of two binary numbers, 10100011 by 1011.
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Q10. Show that adding B after A+B+1 restores the original value of A. What should be done with end carry?
| Earning: Approval pending. |
