Maharashtra State Board of Technical Education 2008 B.E Computer Science and Engineering Computer System Architecture ,maharashtra state board - Question Paper
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(b) iv, v, ii, i, iii
(c) iii, i, ii, iv, v
(d) i, ii, iii, iv, v
(e) ii, iii, i, v, iv.
15. Which of the subsequent binary number is equivalent to 20?
(a) 10100
(b) 100
(c) 000010
(d) 11111
(e) 10111.
16. The Hexadecimal number system has a radix of
(a) 10
(b) 2
(c) 8
(d) 16
(e) 5.
17. What is equivalent of -3510 in 8-bit 2's complement representation?
(a) 01011101
(b) 11011111
(c) 11011101
(d) 00101101
(e) 11001101.
18. In a Hamming code for transmitting a data of 4-bit, how many parity bits are used?
(a) One
(b) Two
(c) Three
(d) Four
(e) Zero.
19. In a Karnaugh map the adjacent minterms can be combined only if the configuration of
(a) 2
(b) 4
(c) 2 x n
(d) 2n
(e) 2n-1.
20. State the purpose of stack pointer(sp) register?
(a) It is used for accessing strings
(b) It is used for accessing memory
(c) It is used for accessing stack
(d) It is used for accessing data segment
(e) It is used for accessing code segment.
21. Which of the subsequent is not involved in memory write operation?
(a) MAR
(b) PC
(c) IR
(d) MDR
(e) Data Bus.
22. In accessing a disk block the longest delay is due to
(a) Rotation time
(b) Seek time
(c) Transfer time
(d) Clock speed
(e) Access time.
23. The read/write line
(a) Belongs to the data bus
(b) Belongs to the control bus
(c) Belongs to the address bus
(d) Belongs to CPU bus
(e) Belongs to System bus.
24. How many flip-flops are needed to implement divide-by-10 in a Johnson counter configuration?
(a) 10 flip-flops
(b) five flip-flops
(c) 20 flip-flops
(d) one flip-flop
(e) nine flip-flops.
25. For shifting a 16-bit binary number into a 16 flip-flop serial shift register how many clock pulse will be required?
(a) two pulses
(b) four pulses
(c) eight pulses
(d) 16 pulses
(e) 32 pulses.
26. A counter that counts from 0 to seven is called
(a) mod- eight counter
(b) mod- seven counter
(c) mod-10 counter
(d) mod- six counter
(e) mod- nine counter.
27. A 2-to-4 decoder has two inputs A and B, where B is the lowest significant bit and four outputs F0, F1, F2 and F3 where F0 is the lowest significant bit. elaborate the valid set Boolean logic expressions that could implement the decoder's functionality?
(a) F0 = A'. B'; F1 = A'. B; F2 = A . B'; F3 = A . B
(b) F0 = A'. B'; F1 = A . B'; F2 = A'. B; F3 = A . B
(c) F0 = A . B ; F1 = A'. B; F2 = A . B'; F3 = A'. B'
(d) F0 = A . B ; F1 = A . B'; F2 = A'. B; F3 = A'. B'
(e) F0 = A'. B'; F1 = A .B; F2 = A'. B; F3 = A . B'.
28. Consider the circuit diagram showing the connection of a JK-flip-flop and the timing diagram provided below:
elaborate the respective values of Q1 at A, B, C and D?
(a) A – 0 B – 0 C – 0 D – 0
(b) A – 0 B – 0 C – one D – 0
(c) A – one B – one C – 0 D – 1
(d) A – 0 B – one C – one D – 1
(e) A – one B – 0 C – one D – 0.
29. If A, B and C are Boolean inputs to the logic circuit shown here,
then what does the function F(A, B, C) compute?
(a) F = A
(b) F = AB'C
(c) F = ABC
(d) F = (A+B)C
(e) F = (A+B')C.
30. Given beneath are a few statements associated with computer memory. Identify the accurate statements from among them.
(a) SRAM is more dense than DRAM
(b) DRAM is used as cache memory
(c) SRAM is slower than DRAM
(d) SRAM has a lower cost than DRAM
(e) SRAM does not require refreshing like DRAM.
END OF part A
part B : issues (50 Marks)
• This part consists of ques. with serial number one – five .
• ans all ques..
• Marks are indicated against every ques..
• Detailed workings should form part of your ans.
• Do not spend more than 110 - 120 minutes on part B.
1. a. discuss the stack organization in CPU. ( 5 marks)
b. Convert the subsequent numerical arithmetic expression three + four * two / (1-5)^2 into reverse Polish notation and write the stack operations for it. ( 5 marks)
2. a. What must be the address field of an indexed addressing mode instruction be to make it the identical as a register indirect mode instruction? ( 5 marks)
b. An instruction is started at location 300 with its address field at location 301.The address field has the value 400. A processor register R1 contains the number 200.
Evaluate the effective address if the addressing mode of the instruction is
i. Direct
ii. Immediate
iii. Relative
iv. Index with R1 as index Register. ( 5 marks)
3. Define Johnson counter? Design a five bit Johnson counter and discuss its operation? ( 10 marks)
4. Design a clocked sequential circuit whose state diagram is provided in the figure using JK
flip-flops. Tabulate the state table and excitation table?
( 10 marks)
5. Design a combinational circuit with 3 inputs x, y, z and 3 outputs A, B, C. When the binary input is 0, 1, 2, three the binary output is equal to one if the input variable is 4, 5, 6, seven the binary output is 1 less than the input. ( 10 marks)
END OF part B
part C : Applied Theory (20 Marks)
• This part consists of ques. with serial number six - seven .
• ans all ques..
• Marks are indicated against every ques..
• Do not spend more than 25 -30 minutes on part C.
6. Explain Processor Examples-68000 Interrupt Structure, Power PC Interrupt Structure? ( 10 marks)
7. Briefly discuss the Handshaking method of asynchronous data transfer. How is it advantageous over the strobe method? ( 10 marks)
END OF part C
END OF ques. PAPER
| Earning: Approval pending. |
