Maharashtra State Board of Technical Education 2008 B.E Computer Science and Engineering Computer System Architecture ,maharashtra state board - Question Paper
Saturday, 04 May 2013 10:45Web
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part A : Basic Concepts (30 Marks)
• This part consists of ques. with serial number one - 30.
• ans all ques..
• every ques. carries 1 mark.
• Maximum time for answering part A is 30 Minutes.
1. A major advantage of direct mapping of a cache is its simplicity. The main disadvantage of this organization is that
(a) It does not allow simultaneous access to the intended data and its tag
(b) It is more expensive than other kinds of cache organizations
(c) The cache hit ratio is degraded if 2 or more blocks used alternately map onto the identical block frame in the cache
(d) Its access time is greater than that of other cache organizations
(e) The number of blocks needed for the cache increases linearly with the size of the main memory.
2. A hypothetical processor communicates with its memory and peripheral over an 8-bit data bus and a 16-bit address bus. It contains an 8-bit accumulator A and 2 16-bit registers: program counter PC and index register X. The opcode of every instruction is 1 byte (8 bits) long. presume that any internal processor time is negligible, and that the time to address memory and transfer 1 byte in either direction over the data bus equals unity (one memory cycle).
The time taken to fetch and execute the 3-byte instruction "store A in a few address indexed by X" is
(a) 3
(b) 4
(c) 5
(d) 6
(e) 7.
3. If a cache access requires 1 clock cycle and handling cache misses stalls the processor for an additional 5 cycles, which of the subsequent cache hit rates comes nearest to achieving an avg. memory access of two cycles?
(a) 75
(b) 80
(c) 83
(d) 86
(e) 98.
4. The CPU deals with every instruction in a cycle. The sequence of instructions to carry out 1 machine instruction is called the instruction or machine cycle. The 1st action is to fetch the instruction from memory and then the program counter is updated (reset). The other 3 phases of the machine cycle in the accurate order are:
(a) Decode the instruction; Execute the instruction; Transfer the data
(b) Decode the instruction; Transfer the data; Execute the instruction
(c) Execute the instruction; Decode the instruction; Transfer the data
(d) Transfer the data; Execute the instruction; Decode the instruction
(e) Only transfer the data.
5. A 4-bit shift register is to be made using D flip-flops. How many flip-flops will be required?
(a) One
(b) Two
(c) Three
(d) Four
(e) Five.
6. Consider the subsequent 4 operations.
RAID 0 RAID one RAID three RAID 5
(I) (II) (III) (IV)
The operation of mirroring the image of 1 hard disk to a different is done by
(a) Only (I) above
| Earning: Approval pending. |
