Andhra University 2005-2nd Year B.Tech Information Technology Forth Semester - VHDL (ELECTIVE-II) - Question Paper

MODEL PAPER

B. Tech (IT) Degree exam

Forth Year - 2nd Semester

VHDL (ELECTIVE-II)

Time: three hrs
Max Marks: 70

First ques. is Compulsory

ans any 4 from the remaining ques.

All ques. carry equal marks

ans all parts of any ques. at 1 place

1. (a) provide a typical design flow for designing VLSI IC circuits
(b) Distinguish ranging from top - down and bottom - up design methodologies for digital design
(c) describe the logic value set and data kinds such as any nets, registers and numbers
(d) define the port connection rules in a module instantiation
(e) define fall and turn-off delays in the gate-level design
(f) define the continuous assignments (assign) statement and restrictions on the assign statement
(g) discuss the significance of structured procedures always and initial in behavioral modeling

2. A 4-bit ripple carry adder (Ripple Add) contains 4 1-bit full adders (FA).
(a) describe the module FA Do not describe the internals or the terminal list.
(b) describe the module Ripple Add. Do not describe the internals or the terminal list. Istantiate 4 full adders of the kind FA in the module Ripple Add and call them fa0,fa1,fa2, and fa3.

3. Declare the subsequent variables in Verilog.
(a) (i) An 8-bit vector net called a_in.
(ii) A 32-bit storage register called address. Bit 31 must be the mot significant bit. Set the value of the register to a 32-bit decimal number equal to 3.
iii) A time variable called snap_shot.
(iv) A memory MEM containing 256 words of 64 bits every.
(b) What would be the output effect of the subsequent statements?
(i) latch = 4'd12;
$display ("The current value of latch = %b\n", latch);
(ii) in_reg = 3'd2;
$monitor ($time, "In register value = %b\n", in_reg[2:0]);
(iii) describe MEM_SIZE 1024
$display ("The maximum memory size is %h", MEM_SIZE);

4. (a) A 4-bit parallel shaft register has 10 pins as shown in the figure beneath. Write the module definition for this module shift_reg. Include the list of ports and port declarations. You do not need to show the internals.
-----DIAGRAM-----

(b) Declare a top-Level module stimulus. describe REG_IN (4bit) and CLK (1 bit) as reg register variabes and REG_OUT (4bit) as wire. Instantiate the module shift_reg and call it sr1. Connect the ports by orderedlist.

5. Design a 2-to-1 multiplexer using bufif0 and bufif1 gates as shown beneath.
-----DIAGRAM-----
The delay specification for gates b1 and b2 are as follows.

Min Type Max
Rise 1 2 3
Fall 3 4 5
Turnoff 5 6 7
6. A full subtractor has 3 1-bit input x,y, and z (previous borrow) and 2 1-bit outputs D(difference) and B(borrow). The logic equations forD and B are as follows:
D=x'.y'.z+x'.y.z' +x.y'.z'+x.y.z
B=x'.y+x'.z+y.z
Write the full Verilog description for the full subtractor module including I/Oports (Remembei that + in logic equations corresponds to a logical or operator ( ) in dataflow). Instantiate the subtractor inside a stimulus block and test all 8 possible combinations of x,y, and z provided in the subsequent truth table.

X Y Z B D
0 0 0 0 0
0 0 one 1 one
0 one 0 one 1
0 one 1 one 0
1 0 0 0 one
1 0 one 0 0
1 one 0 0 0
1 one 1 one 1

7. (a) Design a negative edge-triggered D-flipflop (D_FF) with synchronous clear, active high (D_FF clears only at a negative edge of clock when clear is high). Use behavioral statements only. (Hint: Output q of D_FF must be declared as reg) Design a dock with a period of 10 units and test the D-FF.
(b) Design the D-flipflop in exercise seven with asynchronous clear (D_FF clean whenever clear goes high. It does not wait for next negative edge). Test the D-FF.

8. (a) describe a task to calculate the factorial of a 4-bit number. The output is a 32-bit value. The outcome is assigned to the out put after a delay of 10 time units.
(b) describe a task to computer even parity of a 16-bit number. The outcome is a 1-bit value that is assigned to the output after 3 positive edges of clock (Hint: Use a repeat loop in the task).

Earning:   Approval pending.