Andhra University 2006 B.E Information Technology COMPUTER SCIENCE

Bit Position 15 14 … … nine eight … … … 0

s

e

m

Sign Exponent Mantissa



Let s, e, and m be the numbers represented in binary in the sign, exponent, and mantissa fields respectively. Then the floating point number represented is:







What is the maximum difference ranging from 2 successive real numbers representable in this system?
2 –40
2-9
2 22
2 31



44. A 1-input, 2-output synchronous sequential circuit behaves as follows:

Let Z k n k denote the number of O's and 1's respectively in initial k bits of the input

(Z k + n k = k). The circuit outputs 00 until 1 of the subsequent conditions holds.
Z k – n k = 2. In this case, the output at the k-th and all following clock ticks Is 10
N k – Z k = 2. In this case, the output at the k-th and all following clock ticks is 01.

What is the minimum number of states needed in the state transition graph of the above circuit?
5
6
7
8



45. The literal count of a boolean expression is the sum of the number of times every literal appears in the expression. For example, the literal count of (xy + xz') is 4. elaborate the minimum possible literal counts of the product-or-sum and sum-of product representations respectively of the function provided by the subsequent Karnaugh map? Here, X denotes "don't care"



xy ®

00

01

11

10

Zw ¯









00

X

1

0

1

01

0

1

X

0

11

1

X

X

0

10

X

0

0

X












(11, 9)
(9, 13)
(9, 10)
(11, 11)

46. Consider the ALU shown beneath.



If the operands are in 2's complement representation, which of the subsequent operations can be performed by suitably setting the control lines K and C o only (+ and -denote addition and subtraction respectively)?
A+ B, and A-B, but not A+ one
A+B, and A+ 1, but not A-B
A + B, but not A - B, or A + one

(d) A+ B, and A-B, and A+ one

47. Consider the subsequent circuit composed of XOR gates and non-inverting buffers.



The non-inverting buffers have delays d one = two ns and d two = four ns as shown in the figure. Both XOR gates and all wires have zero delay. presume that all gate inputs, outputs and wires are stable at logic level 0 at time 0. If the subsequent waveform is applied at input A, how many transition(s) (change of logic levels) occur(s) at B during the interval from 0 to 10 ns ?

Earning:   Approval pending.