Andhra University 2007 B.E Electronics & Tele-Communication Engineering VLSI Design Techniques - Question Paper

First ques. is compulsory
ans any 4 out of the remaining ques.
All ques. carry equal Marks

1
a) What do you mean by compound gate?
b)Draw Nand Gate Pull-down Truth Table?
c)what is Flower-Nordheim Tunneling?
d)List any 4 materials used as masl.
e)List the CMOS layout rules for N-Well Layer
f)what is meant by Delay Fault Testing?
g)what is virtual grid symbolic layout?

2)
a)Design a behavioural model for the sum gate of the adder.
b)Calculate the native threshold voltage for an n-transistor at 300degreeK for a process with a Si substrate with N4=1.80*10pow(16),gate oxide with thickness 200a(assume $ms=-0.9V,$fc=0)

3
a)Explain why substrate and well contacts are important in Mask.
b)Explain how the shape of the i/p waveform to a CMOS logic gate alters the delay through the gate.

4)
a)Design a 32 - i/pNOR gate tjat os optionalised for speed and density. Using gate-array complementry login cells with Wr=50u, Ln=1u, Wp=50u,lp=1u
b)In a CMOS circuit when synchronization failure will occur? How to overcome it?

5)
a) A precharge bus has a loading og 10PF . At a point in the clock cycle , 64 resistors in the transmisssion gates on their inputs turn on. THe i/p load of every resistors is 0.1PF. compute the change in precharge voltage.What would be an option approach?
b) discuss the characteristics of MOS-capacitor.
6)
a)List and discuss any 2 scaling models.
b)Derive the scaled values for speed and power density for a process choice that scales the voltage and the gate lengtj

7)
a)with the help of an example discuss built in self test.
b)Explain ultra test Systems.

8)
a)Thermal aspects of processing
b)symbolic diagram
c)Limitation of scaling

Earning:   Approval pending.