Andhra University 2007 B.E Electronics & Tele-Communication Engineering VLSI Design Techniques (Revised Syllabus) - Question Paper

ans ques. No.1 and any 4 from the ramaining
All ques. carry equal marks

1)
a)state moore's legal regulations
b)what is the significance of threshold voltage and what parameterrs influence the threshold voltage?
c)what are the basic layers in MOS circuits
d)drw the stick diagram for CMOS inverter
e)what is wiring capacitance
f)what is switch logic?
g)what is built in self-test?

2)
a)explain the design flow of a VLSI system
b)explain th CMOS fabrication process in detail. presume h-well process

3)
a)what are the various scaling models and discuss the scaling factors for device parameters?
b)what are the limitations of scaling?

4)explain about the subsequent
a)lambda-bared design rules
b)double metal process rules

5)
a)describe the calculation of area capacitance of a layer
b)how is the CMOS inverter delay estimated?

6)
a)discuss the structured design of four way MUX and draw a stick diagram and layout for standard cell using nMOS
b)explain CMOS dynamic memory cell learn and write operations

7)
a)explain the design for testability
b)explain the clocking strategies used in login design

8write short notes on the subsequent
a)ultra fast systems
b)aspects of design tools
c)thermal design consideration

Earning:   Approval pending.