Deemed University 2011 B.Tech Electrical and Electronics Engineering University: Lingayas University Term: V Title of the : Digital electronics and logic design - Question Paper
Roll No. ..
Lingayas University
B.Tech. 2nd Year (Term V)
Examination Feb 2011
Digital Electronics & Logic Design (EE - 205)
[Time: 3 Hours] [Max. Marks: 100]
Before answering the question, candidate should ensure that they have been supplied the correct and complete question paper. No complaint in this regard, will be entertained after examination.
Note: Attempt five questions in all. All questions carry equal marks. Question no. 1 is compulsory. Select two questions from Section B and two questions from Section C.
Section A
Q-1. Part A
Select the correct answer of the following multiple choice questions. [10x1=10]
(i) A bubbled OR gate is equivalent to a
(a) AND gate (b) NAND gate (c) NOR gate (d) X-OR gate
(ii) The simplified form of the Boolean expression (X+Y+Z) (X+Y+Z ) (X + Y + Z)
(a) X'Y+Z (b) X+YZ (c) XY+Z (d) XY+Z
(iii) The 7-bit Hamming code is used to transmit
(a) 3 Data bits (b) 4 Data bits (c) 7 Data bits (d) No data bits
(iv) The terms which cannot be combined further in the tabular method are called
(a) Implicants (b) Prime implicants
(c) Essential prime implicants (d) Selective prime impliacnts
(v) Which logic gate is a basic comparator?
(a) NOR gate (b) NAND gate
(c) XOR gate (d) XNOR gate
(vi) The race around condition occurs in J-K flip flop when
(a) Both Inputs are zero (b) Both inputs are one
(c) The inputs are complementary (d) Any one of the input is present
(vii) The number of Flip flops required for a Mod-12 Johnson counter is
(a) 4 (b) 6 (c) 12 (d) 24
(viii) The logic family that has the highest fan out is
(a) TTL (b) IIL (c) MOS (d) CMOS
(ix) The fastest ADC is
(a)
counter type (b) Flash type
(c) Successive approximation type (d) Dual slope type
(x) A ROM whose contents can be selectively erased
(a) an MROM (b) a PROM (c) an EPROM (d) an EEPROM
Q-1. Part (B)
(i) Perform the following subtraction in 8421 code using the l0s complement method 206.4-507.6
(ii) Design a 4-bit Gray to Binary code converter. [2x5=10]
Section - B
Q-2. (a) With the help of neat diagram, explain the working of the Successive Approximation type ADC. [10]
(b) Explain the specifications of Digital to Analog converter. [10]
Q-3. (a) Explain the architecture of PLA using a neat diagram and show how the PLA would be programmed to implement Sum and Carry outputs of a Full adder. [10]
(b) What is FPGA? Draw the neat diagram and explain its working? [10]
Q-4. (a) Write short notes on interfacing of various logic families?[10]
(b) With the help of a neat diagram, explain the working of 2-input TTL NAND gates? [5]
(c) Explain the working of two input ECL OR/NOR gate? [5]
Section C
Q-5. (a) Show that both NAND & NOR gates are Universal gates? [10]
(b) The message below coded in the 7-bit hamming code is transmitted through a noisy channel. Decode the message assuming that at most a single error occurred in each word. [10]
1001001, 0111001, 1110110, 0011011
Q-6. (a) Minimize the following logic function using K-map and implement the real minimal expression in universal logic [10]
F(A,B,C,D)=(A+B+C+D) (A+C+D) (A+B+C+D)(B+C)(B+C)(A+B)(B+D)
(b) Using the Quine-Mcculuskey method minimize the following expression [10]
F=Sm(0,1,2,8,9,15,17,21,24,25,27,31)
Q-7. (a) Design 16:1 multiplexer using 4:1 multiplexer modules. [10]
(b) Explain the working of BCD adder with an example? [10]
Q-8. (a) Design a J-K counter that goes through states 3,4,6,7 and 3 Is the counter self starting? Modify the circuit such that whenever it goes to an invalid state it comes back to 3. [10]
(b) With the neat diagram explain data transmission in shift registers. [10]
| Earning: Approval pending. |
