Deemed University 2009 A.M.I.E.T.E Electronics & Communication Engineering Digital hardware design – et (old scheme) - Question Paper

AMIETE – ET (OLD SCHEME)

Code: AE27 Subject: DIGITAL HARDWARE DESIGN
Time: three Hours Max. Marks: 100

NOTE: There are nine ques. in all.
· ques. one is compulsory and carries 20 marks. ans to Q. 1. must be written in the space given for it in the ans book supplied and nowhere else.
· Out of the remaining 8 ques. ans any 5 ques.. every ques. carries 16 marks.
· Any needed data not explicitly given, may be suitably presumed and said.


Q.1 select the accurate or the best option in the following: (210)

a. An electronic circuit in which a state switches ranging from 2 distinct states when there is a change in the input states or conditions is called
(A) Digital circuit. (B) Analog circuit.
(C) Mixed circuit. (D) None of the above.

b. If an entity is a gate level model with a rise and fall delay, values for the rise and fall delays could be passed into the entity using
(A) Driver. (B) Bus.
(C) Generics. (D) Process.

c. VHDL stands for
(A) Verilog Hardware Description Language.
(B) Very High Speed Digital Language.
(C) Versatile Hardware Description Language.
(D) Very High Speed Integrated Circuit Hardware Description Language.

d. The ASSERT statement in VHDL checks the value of a
(A) Boolean Expressions. (B) Complex Expressions.
(C) Textual String. (D) Both (A) and (B).

e. In an VHDL, signal represents the
(A) Interconnection wires. (B) Components.
(C) Ports. (D) Temporary data.

f. (XY)5=(YX)4, then
(A) X=4, Y=3. (B) X=4, Y=3.
(C) X=6, Y=3. (D) X=3, Y=4.



g. Implementation of a switching function through a 4:1 MUX is shown in Fig.1. Identify the switching function
(A)

Earning:   Approval pending.