KIIT University 2007 B.Tech Electronics and Tele-Communication Engineering MICROPROCESSOR - Question Paper
MICROPROCESSOR
---- fifth SEMESTER----------
FIFTH SEMESTER EXAMINATION-2007
K-iLZkgjujRegular & Back)
MP EC 502 (EE, E&TC, E&EE, IT)
Full Marks: 70 Time: 3 Hours
Answer any SIX questions including Question No.l which is compulsory.
The figures in the margin indicate full marks.
Candidates are required to give their answers in their own words as far as
practicable and of all parts of a question should be answered at one place only.
1. [1x10
i) The content of the Accumulator in 8085 after ADD operation is 11011011. What would be the status of zero flag and parity flag?
ii) What is the use of READY pin?
iii) If contents of [SP] register in 8085 is presently 2444 H.
Then after PUSH H instruction is executed, what would be the content of [SP] ?
iv) What are the Addressing Modes used in the instructions (a) LXI H, 6000 H (b) STAX D
v) How many address pins are available in a 2764 (8Kx8) EPROM chip?
vi) Name the machine cycles used to fetch and execute the instruction ADD M.
vii) What would be the control word to set bit PC4 of Port C in 8255 in the BSR Mode?
viii) How many 8259 chips would be required to service upto 64 number of interrupt devices?
ix) Determine OCW1 for a 8259 to unmask only IR6 and IR7 and mask the rest of interrupt inputs.
(i)
KJIT-U/2007/Autumn End Semester Examination-2007
x) Find out the 20 bit physical Address in a 8086 system if the contents of[CS] = 4000 H and [IP] = 0004 H.
2. a) What are the roles of Accumulator and Program Counter in the 8085 Internal Architecture?
b) What are the different Control and Status signals available in a 8085 Microprocessor?
c) What is the use of Stack in a 8085 Microprocessor system?
d) What is the difference between memory mapped I/O and I/O mapped I/O?
3. a) Describe the various Addressing Modes of 8085 with suitable examples.
b) Draw the Timing diagram for thelNA machine cycle for fetching and executing a one byte RST opcode and explain the various signals shown in the Timing diagram.
c) Explain the Rotate Instructions available under 8085 Instruction set with proper diagrams showing the bit movement.
4. a) What is a Two Pass Assembler?
b) What are the various Debugging methods used in Software Development?
c) A crystal of 4 MHz is connected to pins X1 and X2 of a 8085 Microprocessor. In this system, a Delay subroutine as given below is to be implemented.
I
Delay: LXI B, 0258 H 10 LOOP: DCX B 6
MOV A, C 4 ORA B 4
JNZ LOOP 10/7 RET 10
Find out the exact time delay that would be generated with the above Delay subroutine.
(2)
d) Design a suitable interface circuit with a 3 to 8 decoder chip to interface the following memory chips to a 8085 Microprocessor a 2764 EPROM (8Kx 8) chip and a 6264 RAM (8Kx 8) chip.
EPROM address has to start from 0000H and RAM address has to start from 8000H.
IF*
Show the memory map.
5. a) What is the advantage of the Interrupt driven data
transfer scheme over Asynchronous data transfer scheme?
b) How can the programmer selectively mask some of the Hardware interrupts of a 8085 Microprocessor? What could be the necessity for such masking?
[2+2
c) In the 8085 interrupt system, how is the INTR interrupt used? Explain with suitable circuit diagram.
6. a) Frame a Control Word for the following configuration
of Ports of 8255
Port A as input Port in Mode-1
Port B as output Port in Mode-0
Port Caslnput and rest pins of Port C as output
b)
Find the Address of Port A, Port B and Port C of 8255 in the configuration given above.
0)
KUT-U/2001/Autumn End Semester Examination-2007
c) Describe the various handshaking signals in which Port A of 8255 is configured as an Input Port in the handshake/strobed I/O Mode (i.e. MODE-1)
d) Explain with proper diagram how a 8212 can be configured in input mode (i.e. Mode 0)
7. a) Describe the sequence of operation of a 8259 when a device connected to IR2 pin requests to interrupt the processor, when IR6 is being serviced.
b) Frame the ICW1 and ICW2 for a single 8259 chip in a 8085 system with the following parameters.
Call Address for IR0 to be placed at F000H
Call Address Interval of 4
Edge Triggered
c) Determine the Mode word for 8251 to transmit characters with the following parameters.
Async Mode with 9600 baud
(Clk freq at TxC is 153.6 KHz)
Char length = 7 bits and 2 Stop bits
No parity check
8. Write short notes on any Three. [4 x
a) Assembler Directives
b) Framing in serial data transmission
c) Instruction Queue of8086
d) Control flags of 8086
KIlT-lJ/2007/Autumn End Semester Examination-2007
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| Earning: Approval pending. |
