How To Exam?

a knowledge trading engine...


KIIT University 2008 B.Tech Electronics and Tele-Communication Engineering Computer system architecture - Question Paper

Thursday, 24 January 2013 04:00Web


see the attachments beneath
use picasa for better view

- E-TC i3ry    w-b reck fRfgaUr

%\1/    CSACS4M

<EAEF. EAIC. n>

SIXTH SEMESTER EXAMINATION-2008

COMPUTER SYSTEM ARCHITECTURE

[ CS 604 ]

Full Marks: 70    Time: 3 Hours

Ans*vr any SVC questions induing Quart#* M>./ trhuri it cempuiserf.

The figures in the margin indicate fun marks.

Candidates are required to give their answer* in their own worth as far as

*"d of ail oartt of*    should he answered at one place onto.

1. a) What is Register addressing mode? How many 12*10 memory reference is required for this addressing mode?

b)    What is zero address instruction format? Explain with an example.

c)    What is Hit ratio and miss penality?

d)    Define speed up ratio and what is time space diagram?

e)    Whatisthefun<tonofmkroiitine?

f)    Write the difference between von-neuman and non-von-neuman architecture.

g)    What is locality of reference?

h)    What is write through protocol and write back protocol?

0)

K!iTU/2G03/Spring Lnd    Examined or 2008


i) What <& DMA data transfer?

j) Whs! are the different page replacement algorithm? Explain LRU.

?. a) Why addressing mode is used? Discuss different addressing mode of instruction execution with suitable example.

ii) What is microprogram control uni? Explait each block and operation of microprogrammed control unit

3.    a) Why can trtil b us is bidredional? Explain the three bus

architecture inside CPUwith suitable diagram.

b) Wrfothswrtrolsignalsfortheinstrudiongivenbebw in three bus and single bus architecture.

AOD R,. (RJ, R,

where R, and R. are the source and R, is the destination.

4.    a) What is mapping technique? Ilustrate the associative

and set associative mapping technique in cache memory with Suitable example.

b) Oesign the memory of 1024 x B using 128 * 8 RAM ctipand5128 ROM chip vritti proper diagram.

5.    a) What is pipeline hazards? How data hazards can be detected? Explain with proper diagram.

b) A non pipeline system lakes SOns to perform a task. The same task can be processed In a fwe segment pipelined system with a dock cycle of 10 ns Determine speed up of the pipeline for 200 task.

6.    a) Statethebooth'sAlgorithmformuliiplication.Multiply

the following no using the booth's multiplication algorithm.

(-8)'(7)

b) Explain about the ftynn's classification of computer

7.    Distinguish and differentiate between the following (I) RISC Vs CISC

(ii) Array processor Vs Vector processor

6 Write short notes on (any two).

a)    Memory Weriearing

b)    Virtual memory

c)    Arithmatic pipeline and Instruction pipeline

X X X X X 01

urt-uiiteiGrat W.Tunr<i**<l







Attachment:

( 0 Votes )

Add comment


Security code
Refresh

Earning:   Approval pending.
You are here: PAPER KIIT University 2008 B.Tech Electronics and Tele-Communication Engineering Computer system architecture - Question Paper