Jawaharlal Nehru University (JNU) 2008-1st Sem B.Tech R05310201 Set No1,III Supplimentary s,,COMPUTER ORGANISATION - Question Paper

Code No: R05310201 Set No. 1
III B.Tech I Semester Supplimentary Examinations, February 2008
COMPUTER ORGANISATION
( Common to Electrical & Electronic Engineering, Electronics &
Communication Engineering, Electronics & Instrumentation Engineering,
Electronics & Control Engineering and Electronics & Telematics)
Time: three hours Max Marks: 80
ans any 5 ques.
All ques. carry equal marks
? ? ? ? ?
1. (a) discuss about sign magnitude and 2’s complement approaches for representing
the fixed point numbers. Why 2’s complement is preferable.
(b) provide means to identify whether or not an overflow has occurred in 2s comple-
ment addition or subtraction operations. Take 1 example for every possible
situation and discuss. presume four bit registers.
(c) Distinguish ranging from tightly coupled microprocessors and tightly coupled Mi-
croprocessors. [16]
2. (a) discuss about stack organization used in processors. What do you understand
by register stack and memory stack? [10]
(b) discuss how X=(A+B)/(A-B) is evaluated in a stack based computer. [6]
3. (a) Support or oppose the statement. The control unit is a firmware? [8]
(b) Support or oppose the statement. If we want to add a new machine language
instruction to a processors instruction set, simply write a C program and
compile and store the resulting code in control memory. [8]
4. (a) How many bits are needed to store the outcome addition, subtraction, multipli-
cation and division of 2 n-bit unsigned numbers. Prove. [8]
(b) What is overflow and underflow? What is the reason? If the computer is
considered as infinite system do we still have these issues. [8]
5. (a) discuss how the Bit Cells are organized in a Memory Chip. [8]
(b) discuss the organization of a 1K x one Memory with a neat sketch. [8]
6. elaborate the various types of I/O Communication techniques? elaborate the
relative advantages and disadvantages? Compare and contrast all techniques. [16]
7. discuss the subsequent with related to the Instruction Pipeline
(a) Pipeline conflicts
(b) Data dependency
(c) Hardware interlocks
(d) Operand forwarding
(e) Delayed load
(f) Pre-fetch target instruction
(g) Branch target buffer
(h) Delayed branch. [8×2=16]
8. (a) elaborate the various physical forms available to establish an inter-connection
network? provide the summary of those. [6]
(b) discuss time-shared common bus Organization. [5]
(c) discuss system bus structure for multiprocessors. [5]

Earning:   Approval pending.