Indian Institute of Technology Mumbai (IIT-M) 2005 M.E Information Technology GATE IT - Question Paper

II. It is possible for process P2 to starve.
Which of the subsequent holds?
(A) Both I and II are actual
(B) I is actual but II is false
(C) II is actual but I is false
(D) Both I and II are false
42. 2 concurrent processes P1 and P2 use 4 shared resources Ri, R2, R3 and R4, as
shown beneath.
P1: P2:
Compute; Compute;
Use Ri; Use Ri;
Use R2; Use R2;
Use R3; Use R3;
Use R4; Use R4;
Both processes are started at the identical time, and every resource an be accessed by only one
process at a time. The subsequent scheduling constraints exist ranging from the access of resources

by the processes:
P2 must complete use of Ri before P1 gets access to Ri.
P1 must complete use of R2 before P2 gets access to R2.
P2 must complete use of R3 before P1 gets access to R3.
P1 must complete use of R4 before P2 gets access to R4.
There are no other scheduling constraints ranging from the processes. If only binary
semaphores are used to enforce the above scheduling constraints, what is the
minimum number of binary semaphores needed?
(A) 1
(B) 2
(C) 3
(D)4
44. We have 2 designs Di and D2 for a synchronous pipeline processor. Di has five pipeline
stages with execution times of three nsec, two nsec, four nsec, two nsec and three nsec while the design D2
has eight pipeline stages every with two nsec execution time. How much time can be saved using
design D2 over design Di for executing 100
instructions?
(A) 214 nsec (B) 202 nsec (C) 86 nsec (D)-200 nsec
45. A hardwired CPU uses 10 control signals Si to SiO in different time steps Ti to T5 to
implement four instructions ii to 14 as shown beneath.
Ti T2 T3 T4 T5
Ii Si, S3,
S5
S2, S4,
S6
Si, S7 Sb S3, S8
1
2
Si, S3,
S5
S8, S9, Sb S5, S6,
S7
S6 Sb
1
3
Si, S3,
S5
S7, S8, Sb S2, S6,
S9
Sb Si, S3
1
4
Si, S3,
S5
S2, S6,
S7
S5, Sb S6, S9 SiO
Which of the subsequent pairs of expressions represent the circuit for generating control signals
S5 and Sb respectively [(Ij+Ik)Tnindicates that the control signal should be generated in time
step Tnif the instruction being executed is If or 1k].
(A) S5 =Ti + 12 .T3&SiO = (Ii + 13) .T4+ (12 + 14) .T5
(B) S5 = Ti + (12 + 14) . T3 & Sb = (Ii + 13) . T4 + (12 + 14) . T5

Earning:   Approval pending.