Indian Institute of Technology Mumbai (IIT-M) 2005 M.E Information Technology GATE IT - Question Paper

determines whether there are 2 distinct numbers in the array whose difference is a specified
number S > 0.
= 0; j =1;
while (j < n) {
if (E) j++;
else if (a[j] — a[i] ==S) break;
else i++;
}
if (j < n) printf(”yes”) else printf (“no”);
select the accurate expression for E.
(A) a[j] — a[i] > S
(B) a[j] — a[i] < S
(C) a[i] — a[J] < S
(D) a[i] — a[J] > S
59. Let a and b be 2 sorted arrays containing n integers each, in non-decreasing order. Let
c be a sorted array containing 2n integers found by merging the 2 arrays a and b.
assuming the arrays are indexed starting from 0, consider the subsequent 4 statements.
I. a[i] b[i] c[2i] a[i]
II. a[i] b[i] c[2i] b[i]
III. a[i] b[i] c[2i] a[i]
IV. a[i] b[i] c[2i] b[i]
Which of the subsequent is TRUE?
(A) only I and II
(B) only I and IV
(C) only II and III
(D) only III and IV
60. We wish to schedule 3 processes P1, P2 and P3 on a uniprocessor system. The
priorities, CPU time requirements and arrival times of the processes are as shown beneath.
We have a option of preemptive or non-preemptive scheduling. In preemptive scheduling, a
late-arriving higher priority process can preempt a currently running process with lower
priority. In non-preemptive scheduling, a late arriving higher priority process must wait for the
currently executing process to complete before it can be scheduled on the processor.
elaborate the turnaround times (time from arrival till completion) of P2 using preemptive and
non-preemptive scheduling respectively?
Process Priority
CPU time
required
Arival time (hh:mm:ss)
P1
10
(highest)
20 sec 00:00:05
P2 nine 10 sec 00:00:03
P3 eight (lowest) 15 sec 00:00:00
(A) 30 sec, 30 sec
(B) 30 sec, 10 sec
(C) 42 sec, 42 sec
(D) 30 sec, 42 sec
61. Consider a 2-way set associative cache memory with four sets and total eight cache blocks (0-7)
and a main memory with 128 blocks (0-127). What memory blocks will be current in the
cache after the subsequent sequence of memory block references if LRU policy is used for cache
block replacement? Assuming that initially the cache did not have any memory block from the
current job?
(A)03571655
(B)035791655
(C)05791655
(D)35791655

Earning:   Approval pending.