Indian Institute of Technology Mumbai (IIT-M) 2008 M.E Information Technology GATE - Question Paper

Indian Institute of Technology Mumbai M.E info Technology GATE ques.

part - A
1. This ques. consists of TWENTY-THREE multiple ques. of 1 mark every. For every
question
(1.1 — 1.23), 4 possible options (A, B, C and D) are given, out of which ONLY 1 is
correct. Indicate the accurate ans in the boxes corresponding to the ques. only on the
FIRST sheet of the ans book.
1.1 The minimum number of cards to be dealt from an arbitrarily shuffled deck of 52 cards to
guarantee that 3 cards are from a few identical suit is
(a) 3
(b) 8
(c) 9
(d) 12
1.2 The determinant of the matrix
2 0 0 0
8 one seven 2.
2 0 two 0
9 0 six 1
(a) 4
(b) 0
(C) 15
(d) 20
1.3 Let S and T be language over ={a,b} represented by the regular expressions (a+b*)* and
(a+b)*, respectively. Which of the subsequent is true?
(a) ScT
(b) TcS
(c) S=T
(d) SnT=Ø
1.4 Let L denotes the language generated by the grammar S - OSO/00. Which of the subsequent
is true?
(a) L = O
(b) L is regular but not O
(c) L is situation free but not regular
(d) L is not situation free
1.5 The number 43 in 2’s complement representation is
(a) 01010101
(b) 11010101
(c) 00101011
(d) 10101011
1.6 To put the 8085 microprocessor in the wait state
(a) lower the HOLD input
(b) lower the READY input
(c) raise the HOLD input
(d) raise the READY input
1.7 Comparing the time Ti taken for a single instruction on a pipelined CPU with time T2 taken
on a non-pipelined but identical CPU, we can say that
(a) Ti = T2
(b) Ti > T2
(c) Ti
(d) Ti is T2 plus the time taken for 1 instruction fetch cycle
1.8 The 8085 microprocessor responds to the current of an interrupt
(a) as soon as the TRAP pin becomes ‘high’
(b) by checking the TRAP pin for ‘high’ status at the end of every instruction every
(c) by checking the TRAP pin for ‘high’ status at the end of the execution of every instruction.
(d) by checking the TRAP pin for ‘high’ status at regular intervals.
1.9 The most improper matching for the subsequent pairs
X: Indirect addressing 1: Loops
Y: Immediate addressing 2: Pointers
Z: Auto decrement addressing 3. Constants
is
(a) X—3 Y—2 Z-i
(b) X—i Y—3 Z-2
(c) X—2 Y—3 Z-i
(d) X—3 Y—i Z-2
1.10 The subsequent C declarations
struct node{
mti:
float j;
struct node *s[iO];
describe s to be

Earning:   Approval pending.