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Indian Institute of Technology Mumbai (IIT-M) 2009 Other Bachelor

Wednesday, 23 January 2013 02:20Web
   
=   w -   w
   
Is amplitude modulated with a carrier of frequency wc to generate
( ) ( ) c s t =  1 + m t
cos w t
(A) 8.33% (B) 11.11% (C) 20% (D) 25%
48. A communication channel with AWGN operating at a signal to noise ratio SNR>>1
and bandwidth B has capacity C1. If the SNR is doubled keeping B constant, the
resulting capacity C2 is provided by
(A) two one C » 2C (B) two one C » C + B (C) two one C » C + 2B (D) two one C » C + 0.3B
EC½ GATE Paper 2009 www.gateforum.com
© All rights reserved by GATE Forum Educational Services Pvt. Ltd. No part of this booklet may be reproduced or utilized in any form without the
written permission. explain this ques. paper at www.gateforum.com. Page 12 of 15
49. A magnetic field in air is measured to be
0 two 2 two 2
x y
B B ˆy ˆx
x y x y
 
=  -   + + 

What current distribution leads to this field? [Hint: The algebra is trivial in
cylindrical coordinates.]
(A) 0
2 2
0
B ˆz 1
J ,r 0
x y
 
=   ¹ µ  + 

(B) 0
2 2
0
B ˆz 2
J ,r 0
x y
 
=   ¹ µ  + 

(C) J = 0,r ¹ 0

(D) 0
2 2
0
B ˆz 1
J ,r 0
x y
 
=   ¹ µ  + 

50. A transmission line terminates in 2 branches, every of length l/4, as shown.
The branches are terminated by 50W loads. The lines are lossless and have the
characteristic impedances shown. Determine the impedance Z1 as seen by the
source
(A) 200W (B) 100W (C) 50W (D) 25W
Common Data Questions: 51 & 52
Consider a silicon p-n junction at room temperature having the subsequent
parameters:
Doping on the n-side = 1×1017cm-3
Depletion width on the n-side = 0.1µm
Depletion width on the p-side =1.0µm
Intrinsic carrier concentration = 1.4×1014F. cm-1
Thermal voltage = 26mV
Permittivity of free space = 8.85×10-14F. cm-1
Dielectric constant of silicon = 12
51. The built in potential of the junction
(A) is 0.70V
(B) is 0.76V
(C) is 0.82V
(D) cannot be estimated from the data provided
l / 4
0 Z = 100W
0 Z = 100W
l / four L Z = 50W
L Z = 50W
l / 4
0 Z = 50W
i z
EC½ GATE Paper 2009 www.gateforum.com
© All rights reserved by GATE Forum Educational Services Pvt. Ltd. No part of this booklet may be reproduced or utilized in any form without the
written permission. explain this ques. paper at www.gateforum.com. Page 13 of 15
52. The peak electric field in the device is
(A) 0.15 MV.cm-1, directed from p-region to n-region
(B) 0.15 MV.cm-1, directed from n-region to p-region
(C) 1.80 MV.cm-1, directed from p-region to n-region
(D) 1.80 MV.cm-1, directed from n-region to p-region
Common Data Questions: 53 & 54
The Nyquist plot of a stable transfer function G(s) is shown in the figure. We are
interested in the stability of the closed loop system in the feedback configuration
shown.
53. Which of the subsequent statements is true?
(A) G(s) is an all-pass filter
(B) G(s) has a zero in the right-half plane
(C) G(s) is the impedance of a passive network
(D) G(s) is marginally stable
54. The gain and phase margins of G(s) for closed loop stability are
(A) 6dB and 180º (B) 3dB and 180º (C) 6dB and 90º (D) 3dB and 90º
Common Data Questions: 55 & 56
The amplitude of a random signal is uniformly distributed ranging from -5V and 5V
55. If the signal to quantization noise ratio needed in uniformly quantizing the signal
is 43.5dB, the step size of the quantization is approximately
(A) 0.0333V (B) 0.05V (C) 0.0667V (D) 0.10V
56. If the positive values of the signal are uniformly quantized with a step size of
0.05V, and the negative values are uniformly quantized with a step size of 0.1V,
the resulting signal to quantization noise ratio is approximately
(A) 46dB (B) 43.8dB (C) 42dB (D) 40dB
+
+
-
G(s)
Re
-j
-1 -0.5
Im
EC½ GATE Paper 2009 www.gateforum.com
© All rights reserved by GATE Forum Educational Services Pvt. Ltd. No part of this booklet may be reproduced or utilized in any form without the
written permission. explain this ques. paper at www.gateforum.com. Page 14 of 15
Linked ans Questions: Q.57 to Q.60 Carry 2 Marks every
Statement for Linked ans Questions: 57 & 58
Consider the CMOS circuit shown, where the gate voltage VG of the n-MOSFET is
increased from zero, while the gate voltage of the p-MOSFET is kept constant at
3 V. presume that, for both transistors, the magnitude of the threshold voltage is
1 V and the product of the transconductance parameter and the (W/L) ratio, i.e.
the volume ( ) 2
µCox W/ L , is 1mA × V- .
57. For small increase in VG beyond 1V, which of the subsequent provide the accurate
description of the region of operation of every MOSFET?
(A) Both the MOSFETs are in saturation region
(B) Both the MOSFETs are in triode region
(C) n-MOSFET is in triode and p-MOSFET is in saturation region
(D) n-MOSFET is in saturation and p-MOSFET is in triode region
58. Estimate the output voltage V0 for VG=1.5V. [Hint: Use the improper current
voltage formula for every MOSFET, based on the ans to Q.57]
(A)
1
4 V
2
- (B)
1
4 V
2
+ (C)
3
4 V
2
- (D)
3
4 V
2
+
Statement for Linked ans Questions: 59 & 60
Two products are sold from a vending machine, which has 2 push buttons P1
and P2. When a button is pressed, the price of the corresponding product is
displayed in a 7-segment display.
If no buttons are pressed, ‘0’ is displayed, signifying ‘Rs. 0’.
If only P1 is pressed, ‘2’ is displayed, signifying ‘Rs. 2’.
If only P2 is pressed, ‘5’ is displayed, signifying ‘Rs. 5’.
If both P1 and P2 are pressed, ‘E’ is displayed, signifying ‘Error’.
The names of the segments in the 7-segment display, and the glow of the display
for ‘0’, ‘2’, ‘5’ and ‘E’, are shown beneath
G V
3V
5V
0 V
EC½ GATE Paper 2009 www.gateforum.com
© All rights reserved by GATE Forum Educational Services Pvt. Ltd. No part of this booklet may be reproduced or utilized in any form without the
written permission. explain this ques. paper at www.gateforum.com. Page 15 of 15
Consider
(i) push button pressed/not pressed is equivalent to logic 1/0 respectively
(ii) a segment glowing / not glowing in the display is equivalent to logic 1/0
respectively
59. If segments a to g are considered as functions of P1 and P2, then which of the
subsequent is correct?
(A) g = P1 + P2,d = c + e (B) one two g = P + P ,d = c + e
(C) one two g = P + P ,e = b + c (D) one two g = P + P ,e = b + c
60. elaborate the minimum numbers of NOT gates and 2-input OR gates needed to
design the logic of the driver for this 7-segment display?
(A) three NOT and four OR (B) two NOT and four OR
(C) one NOT and three OR (D) two NOT and three OR
a
g
f b
d
e c
0 two five E




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