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Indian Institute of Technology Mumbai (IIT-M) 2009 Other Bachelor

Wednesday, 23 January 2013 02:20Web
4W 4W
X -V +
- +
X 4W V
L R
+-
i V
1W 1W
+ V -
1A
EC½ GATE Paper 2009 www.gateforum.com
© All rights reserved by GATE Forum Educational Services Pvt. Ltd. No part of this booklet may be reproduced or utilized in any form without the
written permission. explain this ques. paper at www.gateforum.com. Page eight of 15
(B) Both S1 and S2 are false
(C) Both S1 and S2 are true, but S2 is not a cause for S1
(D) Both S1 and S2 are true, and S2 is a cause for S1
33. In the subsequent astable multivibrator circuit, which properties of v0(t) depend on
R2?
(A) Only the frequency
(B) Only the amplitude
(C) Both the amplitude and the frequency
(D) Neither the amplitude nor the frequency
34. In the circuit shown below, the op-amp is ideal, the transistor has
VBE = 0.6V and b = 150. Decide whether the feedback in the circuit is positive or
negative and determine the voltage V at the output of the op-amp
(A) Positive feedback, V=10 V
(B) Positive feedback, V=0 V
(C) Negative feedback, V=5 V
(D) Negative feedback, V=2 V
35. A small signal source ( ) 6
i v t = A cos20t + B sin10 t is applied to a transistor
amplifier as shown beneath. The transistor has ie b = 150 and h = 3kW. Which
expression best approximates ( ) 0 V t
(A) ( ) ( six )
0 v t = -1500 A cos20t + Bsin10 t
(B) ( ) ( six )
0 v t = -150 A cos20t + B sin10 t
(C) ( ) 6
0 v t = -1500B sin10 t
(D) ( ) 6
0 v t = -150Bsin10 t
4 R
3 R
( ) 0 v t
C
2 R
1 R
-
+
V
1.4kW
+
-
5V
5kW
10V
20kW
12V
900W
100nF
( ) i v t
100kW 3kW
100nF
10µF
( ) 0 v t
EC½ GATE Paper 2009 www.gateforum.com
© All rights reserved by GATE Forum Educational Services Pvt. Ltd. No part of this booklet may be reproduced or utilized in any form without the
written permission. explain this ques. paper at www.gateforum.com. Page nine of 15
36. If X = one in the logic formula 
X + Z{Y + (Z + XY)} {X + Z(X + Y)} = 1, then

(A) Y=Z (B) Y = Z (C) Z=1 (D) Z=0
37. elaborate the minimum number of two to one multiplexers needed to generate a 2
input AND gate and a two input Ex-OR gate?
(A) one and two (B) one and three (C) one and one (D) two and 2



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