Thapar University 2006 B.E Electronics & Tele-Communication Engineering VLSI Circuit Design - Question Paper
Thapar Institute Of Engineering & Technology, Patiala
End Semester Examination, 2006
VLSI Circuit Design (EC 027)
THAPAR INSTITUTE OF ENGINEERING AND TECHNOLOGY, PATIALA
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
EC-027 VLSI CIRCUIT DESIGN (B.E. Vth Sem EC ) [4.12.2006]
TIME: 3 HOURS END SEMESTER TEST MAX.MARKS:45
Instructor: Balwant Singh
Note: L Attempt ANY FIVE Questions Sequentially.
2. Graph sheets may be asked for, if required.
3. AU questions carry equal marks.
4. Make reasonable assumptions for missing information, if any.
QI a) Describe the structure of an n-channel enhancement type MOSFET. What do you understand by flat band voltage? Explain
b) Find the threshold voltage and body factor 7 for an n-channel transistor with an n+ silicon gate if toX = 200 A0, Na = 3 x 1016 cm'3, gate doping, No = 4 x 1019 cm'3, and if the number of positively charged ions at the oxide-silicon interface per area is 1010 cm'2. (3,6)
Q II a) Draw and explain the energy band diagrams of:
i) The combined MOS system.
ii) The MOS structure operating in depletion mode under small gate bias,
b) Consider a process technology for which Lmi = 0.4 nm, tox = Snm,
Un = 450 cm2/Vs , and V, = 0.7 V.
(i) Find Cox and K./.
(ii) For a MOSFET with W/L = 8 nm/0.8|im, calculate the values of Vcs and Vosmin needed to operate the transistor in saturation region with a DC current ID= 100 nA.
(iii) For the device in (ii), find the value of Vgs required to cause the device to operate as a 1000 Cl resistor for very small vDS. (3,6)
Q III a) Discuss with neat labeled diagrams, how an inverter is fabricated in a p-well CMOS process.
b) For a CMOS -2 input NOR gate, draw
i) Circuit diagram ii) typical layout (5,4)
mQ IV: -a) Explain the time domain behavior of a CMOS bistable element along with a circuit diagram.
b) Draw CMOS SR latch circuit based on NOR 2 gates. Give truth table and explain the circuit operation.
c) What is scaling? Describe with the help of examples, different scaling techniques. (3, 3, 3)
Q V a) Discuss physical origin of latch up and give latch up prevention techniques.
b) What are the components of power dissipation in CMOS circuits? Explain in detail.
c) What do you understand by dynamic CMOS Logic? Describe basic CMOS dynamic gate circuit operation.
d) What are BiCMOS circuits? Describe. (3, 3,2,1)
Q VI a) Draw a basic resistive load inverter circuit. Derive expressions for all the critical point voltages and explain typical VTC of a resistive load inverter circuit, b) Calculate tf ,tPHutr& tPLH for the symmetric CMOS inverter.
VDD =5V ; kn= 40|xA/V2,(W/L)n= 4jxm/2m Vtn=l V; kV=16|iA/V\(W/L)i8ym/2jun Vtp=-lV.
Use a load Capacitance of 0.1 pF. (5,4)
Q VII a) Find the depletion region width xj, the depletion region charge Quo threshold voltage with no source to body voltage Vtho > and body factor 7 of a device with following physical parameters
tox = 400 A0; Na = 1.5 x 10 16 /cm3 (substrate acceptor doping); Np = 10 8 /cm3 (gate donor doping); Nss = 5 x 10 10 /cm2(density of singly charged positive surface ions)
b) Calculate the ion implant dose necessary to change the threshold voltage Vtho of the device in (a) above to +1V or to - 4V. Assume 100% ionization of implanted material.
(6, 3)
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