Thapar University 2006 B.E Computer Science Computer System Architecture - Question Paper

Thapar Institute of Engineering & Technology
B.Tech CS (2nd Year)
Final Term exam
CS004 (Computer System Architecture)

Thapar Institute of Engineering & Technology, Patiala End Semester Test

Course Code: CS-004    Date: 16/12/06

Course Name: Computer System Architecture    Time Allowed: 3 Hr.

Max. Marks: 100

Note : Attempt any five questions

Only first five answers will be evaluated

All parts of a question should be attempted at the same place.

Ql.a)    Explain various addressing modes with examples.    (10)

b)    Explain encoder, decoder, multiplexer and de-multiplexer along with one

example of each.    (10)

Q2.a)    What is Direct Memory Access ? Explain its functioning in detail. (5)

b)    Represent the following arithmetic expression in reverse polish notation and diagrammatically perform the stack operation on it

(3 * 4) +(5 * 6)    (5)

c)    Explain control unit of basic computer in detail.    (10)

Q3.a)    A digital computer has a memory unit of 64K X 16 and a cache memory

of IK words. The cache uses direct mapping with a block of four words.

i)    How many bits are there in the tag, index, block size and word field of the address format?    (2)

ii)    How many bits are there in each word of cache. Include a valid bit.

(I)

b)    A computer employs RAM chips of256 X 8 and ROM chips of 1024 X 8.

The computer system needs 2K bytes of RAM . 4K bytes of ROM and four interface units , each with four registers. A memory-mapped I/O configuration is used. The Highest -order bits of the address bus are assigned 00 for RAM ,01 for ROM & 10 for interface registers.

i)    How many ROM & RAM chips are needed.    (1)

ii)    Draw a memory address map for the system.    (2)

iii)    Give the address range in hexadecimal for RAM,ROM and interface.    (2)

b)    Give the flow chart for addition and subtraction operation.    (12)

Explain all the CPU instructions in detail with examples.

a)    IOP

b)    Pipelining

c)    External & internal interrupts

d)    RISC & CISC architecture

(20)

Attachment: thapar-university-2006-b-e-computer-science-25969-1.pdf

Earning:   Approval pending.