Thapar University 2007 B.E VLSI - Question Paper

THAPAR UNIVERSITY PATIALA
DEPARTMENT OF ELECTRONICS AND COMMUNICATION

Thapar University, Patiala Department of Electronics & Communication BE 3^rd Year (EC)

EC-027 VLSI Circuit Design (15-09-07)

Time: 60 min    First Mid Semester Test    MM: 15

Note: Attempt all questions in sequence. Draw neat & labeled circuit diagram wherever necessary.

1.    Derive an expression for switching threshold voltage for a CMOS inverter. (04)

2.    Sketch a transistor level schematic for a single-stage CMOS logic gate for expression F (03)

F = A'BCD + A'BCD + ABCD + ABCD + ABCD + ABCD

Here A" represents the complement of A, B the complement of B, and so forth..

3.    Find Id for a n-channel transistor having a substrate concentration ofNA = 1.4 X lO/m* with p_nCox= = 188nA/V²T W= 6|im, L = 0.6im. d>₀ = 0.99V. V_cs = 1-2V, V_ln = 0.8V. X = 80.8 X 10'³ V*¹. Assuming X remains constant, estimate new value of Id if Vds is increased by 0.5V.    (03)

4.    Find the threshold voltage and body factor yfor a n-channel transistor with a n⁺ silicon gate if to* = 200 angstorms, N_A = 3 X 10^,6cm'^J, gate doping No = 4 X I0¹⁹ cm³and if the number of positively charged ions at the oxide silicon interface per area is 10^,() cm². If Vsb ⁼ 2V, find the value of Vy for n-channel transistor.    (4+1)

Attachment: thapar-university-2007-b-e-25953-1.JPG

Earning:   Approval pending.