Punjab Technical University 2005 M.Tech Electronics and Communication Engineering PARALLEL PROCESSING ECE 513/514 - Question Paper

PARALLEL PROCESSING ECE 513/514 second Sem May 2k5

Max Marks 100

Note: Attempt any 5 ques.. All ques. carry equal marks.


1. Characterize the architectural operations of SIMD and MIMD computers. Distinguish ranging from multiprocessor and multi-computers base on their structures, resources sharing and interprocessor communications. Also discuss the difference ranging from UMA, NUMA and COMA and NORMA computers.

2. (a) elaborate the conditions for parallelism? discuss the detection and implementation of parallelism id detail.
(b) (i) How many legitimate states are there in a four x four switch module, including both broadcast and permutations.? Justify.
(ii) Construct a 64-input omega network using four x four switch modules in multiple stages.

3. (a) discuss different performance metrics and measures and the trade offs among these performance metrics in the situation of cost-effectiveness.
(b) discuss scaled matrix multiplication using global versus local calculation models

4. (a) elaborate the different instruction-set architectures? Compare their characteristics. discuss the inclusion property of data transfer ranging from adjacent levels of a memory hierarchy.
(b) discuss the difference ranging from multipipeline chaining on cray one and cray –MP for executing the code Y (I :N) = S x X (I:N) + Y(I:N)

5. (a) elaborate direct-mapping and associative caches? explain different cache performance problems. What is the requirement of memory interleaving? Differentiate low-order and high-order interleaving.
(b) A computer system has a 128-byte cache. It uses four-way set-associative mapping with 8-byte in every block. The physical address size is 32-bits and the smallest addressable unit is one byte.
(i) Draw a diagram showing the organization of the cache and indicating how physical addresses are related to the cache addresses.
(ii) To what block frames of the cache can the address 000010AF16 be addressed?
(iii) If the addresses 000010AF16 and FFFF7Axy16 can be simultaneously assigned to the identical cache set, what values can the address digits x and y have?

6. (a) elaborate the various weak consistency models? Compare the performance of sequential consistency and weak consistency memory.
(b) How can air-traffic simulation be done on a multicomputer system, using decomposition technique?

7. Explain the structural and operational difference ranging from register-to-register and memory-to-memory architectures in building multipipelined supercomputers for vector processing. Comment on the advantages and disadvantages In using SIMD computers as compared with the use of pipelined super-computers.

8. Write short notes on the following:
(a) Multithreaded calculation model
(b) Delta-parallel and object-oriented models.
(c) Optimizing compiler for parallelism
(d) Multitasking on cray microprocessors.

Earning:   Approval pending.