Himachal Pradesh University (HPU) 2008 B.Tech - university paper

(2058)
5665
B.Tech sixth Semester exam
Computer Architecture (ECE)
Paper-EC-6001
Time Allowed: three Hours Maximum Marks: 100
Note: Attempt five ques. in all, by selecting at lowest one ques. from every of part A , B, C, D and entire section-E.
Section-A

1. a) explain hardwired & microprogramed control units. Also explain their relative merits & demerits.
b) discuss the difference ranging from instruction & microinstruction. Use examples.
[20]
2. Discuss with example the different addressing modes.
[20]
Section-B

3. What is memory hierarchy? discuss in detail virtual memory.
[20]
4. explain different mapping used for cache memory organization.
[20]
Section-C

5. Discuss the different I/O data transfer techniques.Compaire them.
[20]
6. Explain the following: I/O interface, vectored interrupts & bus arbitration.
[20]
Section-D
7. What is pipelining? explain how pipelining processors improves efficiency of calculation. [20]
8. Discuss:
a) Overcoming data hazard with dynamic scheduling.
b) Pipeline hazard. [20]
Section-E
9. Explain:
a) Role of PLA.
b) Need to understand addressing modes.
c) Feature of bit slice processor.
d) Compare ranging from bipolar & mos memory devices.
e) Why cache is faster then RAM.
f) Why semiconductor memories are preferred?
g) Role of DMA.
h) Role of I/O inter face.
i) Serial & parallel standard.
j) Role of Booth’s algorithm. [20]

Earning:   Approval pending.