Himachal Pradesh University (HPU) 2008 B.Tech Computer Science and Engineering COMPUTER ARCHITECTURE - Question Paper

(2057)
5225
B.Tech. IVth Semester exam
COMPUTER ARCHITECTURE (GSE/FT) Paper-IT(ID)-4001
Time : 3 Hours] [Maximum Marks : 100
The candidates shall limit their answers precisely within the answer-book (40 pages) issued to them and no supplementary/ continuation sheet will be issued.
Note : Attempt 5 ques. in all, selecting 1 question'each from part A, B, C and D, and Q. No. nine of part E (compulsory).


Total No. of ques. - 9] (2057)

5225
B.Tech. IVth Semester exam
COMPUTER ARCHITECTURE (CSE/IT) Paper-IT(ID)-4001

Time : 3 Hours] [Maximum Marks : 100

The candidates shall limit their answers precisely within the answer-book (40 pages) issued to them and no supplementary/ continuation sheet will be issued.
Note : Attempt 5 ques. in all, selecting 1 ques. every from part A, B, C and D, and Q. No. nine of part E (compulsory).

SECTION-A
1. (a) discuss quantitative principles of computer design. eight (b) explain an encoding technique for an instruction set.
7.

2. ^a)/t)raw block diagram of memory hierarchy, and
discuss it. 7
npy) discuss classification of instruction set architecture.
Also explain memory addressing techniques. 8

ip. SECTION-B
3^J What is Pipeline architecture ? explain how pipeline is implemented, with reference to MIPS R4000 pipeline. 15

5225/800/GGG/25 [RT.O.

4. (a) explain the concept of instruction level parallelism and
its advantages. 10
(b) discuss how data hazards can be decreased. 5

SECTION-C
5. (a) A block set associative cache consist of a total 128
cache blocks with two blocks per se*. The main memory
contains four K blocks with 16 words per block. Draw a
figure explaining the mapping and show the partitions
of an address into TAG, SET and Word. 10
(b) discuss how cache misses can be decreased. 5

6. ^(a)^Discuss 2 storage, devices in detail. 10
^(b)xExplain how communication takes place ranging from I/O
device and memory. 5

SECTION-D
ly/" explain what is an interconnection network and its
advantages ? Also define 2 schemes-Time shared
common bus and Cross bar switch for inter-connecting
network. ¦ 15

8. (a) explain characteristics of Multiprocessors. 5
(b) What do you mean by Shared memory architecture ?
discuss difference ranging from Shared and Distributed
memory architectures. 10

{Compulsory) 9. discuss all the subsequent briefly : ^(a^, Cache penalty. (by RAM & ROM. " y(cy Set associative mapping. .^/Memory protection. \(pf^Multistage switching network. ^J£) Cache hit-ratio.^ ^i^y^Memory table.
(h) UNIX file system performance.
(i) Synchronization in Multiprocessor,
(j) DLX architecture characteristics.

Earning:   Approval pending.