Jaypee Institute of Information Technology (JIIT) 2008 B.E Electronics
JAYPEE IMVERS1TV OK INFORMATION TKC IINOI.OGY,
WAKNAGHAT, SOI.AN
Brunch: E & C' Semester: VII
Test: 3rd I>ate:2*Nov.'2Mi
Subject: Analog IC Design (Elective) Max. Marks: 30
Subject Credit: 03 (08B71EC409) Max. l ime: lhr.30min.
Attempt any 6 Questions. All arc or equal marks.
I. Calculate (A) r,i (B) Input Resistance Ri (C) Output Resistance Ro (D) Voltage gain of an Emitter Follower. Where po-100, rt,=0t r0->in(miic, lc*100nA, Ri*1KH, Rs=l K'Q.Draw the required figure. (1*5)
2. Draw the small signal model for bipolar transistor and explain its capacitances.
(2+3)
3 Why Wilson current mirror of bipolar is used and how it works. Drive the
formula for its systematic gain error. (1+2+2)
4. Write short notes of MOS folded cascade configuration. (5)
5. Explain working of any ONE topic. (A) VCO, (13) Comparator (5)
6. Draw the schematic of Switched Capacitor amplifier with ideal switch and explain
Its timing diagram. (4+1)
7. Describe the 2*stage MOS operational amplifier with cascadc. (5)
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Earning: Approval pending. |