Jaypee Institute of Information Technology (JIIT) 2008 B.E Supplimentary - MPC - Question Paper
Jaypce Iniversity of Information Technology BTech 3rd Vear<ECK)
Supplementary Kianimlion Dec 2008 C ourse Codc:07B41CI10S
Time :2Hn Test T3: Microprocessors and Controllers Marks: 100 Note: I. Attempt any five questions.
Q 1. (a) |I0 marks) With the help of timing diagrams explain the bus cycle for memory read and write operations for 8086.
<b) 110 marks| Draw and explain the implementation of memory for 81)86 using 32K Hytc components and sepcratc bank decoder.
Q 2. (a) (10 marks) Explain the register architecture of 8086 processor.
(b) 110 marks| Draw the 8086 machine instruction format and explain the structure of all component bytes.
Q3, (a) |10raarks| Describe a programmable interrupt controller 8259A. Mow can the interrupt structure be expanded using 8259A?
(b) 110 marks) Describe DMA transfer in 8086 system using8237 DMA Controller.
Q4. (a) JI0 marks) Describe the structure of the programming command bytes for 8255. Abo explain the inodes of operation.
(b) 110 marks) Describe the pinout, functions and mode 4 operation of 8254 timer counter.
Q 5. (a) 110 marks) Address and data pins in 8086 are multiplexed? How can the CPU 8086 be connected to the address bus and the data bus?
(b) |IOmarks| Draw a basic input interface for reading the 8 bit electromechanical switch. How can yon ensure that the input does not float when the switch b transiting the intermediate positions?
Q 6. {a) (10 marks| Draw a block schematic of the hardware architecture of 8051 and explain functions of each block.
(b) 110 marks) Explain the structure of internal KAM in 8051.
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| Earning: Approval pending. |
