Uttar Pradesh Technical University (UPTU) 2011-1st Sem B.Tech Computer Science and Engineering theory -12 Elecronics Engineering - Question Paper

beneath attachment is the ques. paper of 1st semester electronics engineering (gbtu)

Printed Pages7

|(Following Paper ID and Roll No. to be filled in your Answer Book)

PAPER ID : 3301

B. Tech.

(SEM. I) THEORY EXAMINATION 2011 -12 ELECTRONICS ENGINEERING

Time : 3 Hours    Total Marks : 100

Note AH Sections are compulsory

SECTIONA

1. All parts are compulsory. All questions carry equal marks :

(10x2=20)

a)/What will happen on number of free electrons in a semiconductor on increasing temperature ?

4.5 V zener is rated at 1.5 watt. What is the maximum safe current of the zener ?

What are the PIVs for full wave center tapped transformer and bridge rectifier respectively ?

V(d)What is the biasing condition of base-emitter and collector-base junction in the active region of a CB BJT configuration ?

(e) Write down the h-parameters of a bipolar j unction transistor. Writg.the Shockley's Equation for JFET.

Write the types of MOSFET and their two major differences.

EEC101/KIH-26659    1    [Turn Over

Write the input and output resistance of an ideal operational amplifier.

What are don't care conditions in digital systems ? /'Write-down the three major advantages of digital multimeter over analog multimeter.

SECTIONB

2. Attempt any three parts of the following. All questions carry equal marks:    (10x3=30)

Draw and explain the full-wave bridge rectifier. Also derive the V_dc for it. Sketch v₀ for the network of Figure 1.

Wi

(b) Draw the circuit diagram of a BJT Emitter Bias and derive the expression for Quotient Point. Write its advantage over BJT fixed bias circuit. Also define bias stabilization and stability factors.

Draw the structure of an n-channel JFET and explain its principle of operation. Also draw its drain and transfer characteristics with the help of suitable circuit. Describe how an FET can be used as a voltage controlled resistor.

EEC 10 l/KIH-26659    2

(d) Explain the basic principle of signal display in a CRO. Also describe the method of measurement of frequency, amplitude and phase.

JWhat are universal gates, explain with neat sketch. Minimize and realize f = Z (1,2,5,7,9,11,12,14,15) using one type of universal gates only.

SECTIONC

NoteAll questions are compulsory. All questions carry equal marks.

3. Attempt any two parts of the following. All questions carry equal marks :    (10x5=50)

(a) Design a clamper to perform the function indicated in Figure 2.

				Ideal Diodes	Vo I	30 V
V|	20 V				I
			+		+
			V|	Design	V0
0			t ;___		0			t
						-10 V
	-20 V

(b) Explain the half wave voltage doubler and full wave voltage

doubler with help of suitable diagrams.

EEC101/KIH-26659    3    /Turn Over

(c) For the network of Figure 3, determine the range of and I_L that will result m being maintained at J_0 V. Also determine the maximum wattage rating of diode.

AAAr

V_Z=10V !zm=32 mA

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V4Attempt any two parts of the following. All questions carry equal marks:

xplain the input and output characteristics of a B JT in the comhion emitter configuration*, If the base current in transistor is 30 |uA when the emitter current is 7.2 mA, what are the values of a and P ?

(b) Draw the hybrid equivalent circuit for common base configuration and write the expression for A_;, It, A_v and R.

(cx Determine the following for the voltage divider configuration shown in Figure 4 :

EEC101/KIH-26659    4

-- 1 f-

5. Attempt any two parts of the following. All questions carry equal marks:

(a)    What is the significant of the threshold voltage V_T in (i) depletion mode (ii) enhancement mode MOSFETs ?

(b)    Determine the following for the network of Figure 5 :

gsq    00 DQ

(iii) V_DS    (iv) V_s

(v) V_G    (vi) V_D

EEC 101 /KIH-26659    5    /Turn Over

Draw and explain the voltage divider bias configuration of JFET.

Attempt any two parts of the following. All questions cany equal marks :

Develop a circuit for Y = (A + B)CD Boolean expression using only NAND gates.

ii)rDevelop a circuit for Y = (A + B)C Boolean expression using only NAND gates. xJ&f'What do you mean by literal ?

Minimize the following using K-map technique : f(A, B, C) = Em(l, 3, 6, 7) + Ld(2, 4)

(c) Perform the following:

EEC 10 l/KIH-26659    6

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Earning:   Approval pending.