GITAM University 2005 B.E Electronics

College of Engineering
Gandhi Institute of Technology and Management, Visakhapatnam
(Affiliated to Andhra University)

B.E. (Electronics and Communications Engineering ) 2nd Year
Second Semester exams 2004-2005
(Autonomous Stream)

EC 221 Digital Circuits and Systems

Time: three Hours Max. Marks: 60

1. Answer ques. No. one ( Part – A) and any 4 of the remaining 7 (Part – B)
2. All parts of a ques. must be answered in 1 place, otherwise they will not be valued.
3. Figures in the right hand margin indicate marks allotted.

PART – A

1. Answer the subsequent. 10x2=20

a) Convert AF3B to binary and then obtain its 2’s complement.
b) Express the minterms using minimum number of literals (i) m48 (ii) m19 .
c) Simplify the function using K-map.
F = min term(1,2,3,4,5,6,7)

d) Realize the X-OR function using only four 2 input NAND gates.
e) Draw the 2: one multiplexer realization of Y = AB.
f) What is an open collector TTL gate?
g) Draw the circuit of CMOS NAND gate.
h) Write the excitation Table of J-K flip-flop.
i) Draw the state diagram of the synchronous sequential machine defined by the subsequent state table.

current state Next state Output
X = 0 X = 1 X = 0 X = 1
A B A B A B Y Y
0 0 0 0 0 1 0 0
0 1 0 0 1 1 1 0
1 0 0 0 1 0 1 0
1 1 0 0 1 0 1 0

j) When a race condition will occur in an asynchronous sequential circuit?


PART – B

ans any 4 of the subsequent. If you attempt more than 4 questions, only the 1st 4 in order will be valued.

2. a) A four bit data is encoded using Hamming code and is then transmitted. The received bit stream is 0101100. obtain the fault in the code and accurate it. elaborate the data bits? (5)
b) Express the subsequent function in canonical sum of products form f = ( d+ cd)
(5)

3. a) Prove the subsequent
(ab+bc+ca)' = a'b'+b'c'+c'a' (3)
b) Simplify the logic expression using Quine Mc cluskey method.
f (a,b,c,d) = min term(3,4,5,7,9,13,14,15) (7)

4. a) Implement the subsequent 2 Boolean functions with a PLA
F1 (A,B,C) = ? (0,1,2,4)
F2 (A,B,C) = ? (0,5,6,7) (6)
b) Draw the circuit of TTL NAND gate and discuss. (4)

5. a) Design a J-K Flip-flop using D-FF. (8)
b) What is a shift register? (2)

6. a) Design a synchronous counter to count in the random sequence 1,3,5,7,0,1,3,5,7,0 …… using J-K flip-flop. (8)
b) Define modulus of a counter. (2)

7. a) Minimize the state Table provided below: (7)

current state Next state Output z =
w = 0 w = 1
A B C 1
B D F 1
C F E 0
D B G 1
E F C 0
F E D 0
G F G 0

b) Realize T and D Flip-flops using JK flip-flop. (3)

8. a) An asynchronous sequential circuit is defined by the excitation and output functions.
Y = x1x2'+(x1+x2')y
Z = y
i) Draw the logic diagram of the circuit.
ii) Derive the transition table and output map. (5)

b) How a race free state assignment is achieved. discuss with suitable example. (5)

Earning:   Approval pending.