Annamalai University 2008-3rd Sem B.E Computer Science and Engineering , (/information techology) (ester) coec-304/itec-303 digital logic disign - Question Paper
DIGITAL LOGIC DESIGN
TIME:3HRS
TOTAL NO OF PAGES:3
TOTAL NO OF UNITS:5
TOTAL MAXIMUM MARKS :60
HAVE TO ATTEND full 1 ques. FROM every UNIT.
a few SINGLE ques. IS DIVIDED INTO SUB PART 'a' AND 'b'.
Register Number:
Name of the Candidate :
6 0 6 5 B.E. DEGREE EXAMINATION, 2008
( COMPUTER SCIENCE AND ENGINEERING / INFORMATION TECHNLOGY )
( THIRD SEMESTER )
COEC - 304 / ITEC - 303. DIGITAL LOCIC DESIGN
May ] [ Time : 3 Hours
Maximum : 60 Marks
Answer any ONE full question from each unit. All question carry equal marks.
UNIT-I
1. (a) How do you convert (1832.65) into
(i) Binary.
(ii) Hexa decimal equivalent numbers.
(b) Explain various digital logic families and MOS circuit.
2. (a) Explain various theorems of Boolean algebra
and list the properties.
(b) How NAND and NOR gates and said to be universal gates ? Explain.
UNIT-II
3. (a) What is a dont care term ? How do you
represent SOP form of Boolean expression into POS form.
(b) How do you convert any boolean function into a 2 level NDR function only ? illustrate.
4. With a 6 variable k map. Simplify the following boolean function.
F = em (0,1,2,5,6,7,10,11,16,18,24,27)
ed + (28,29,30)
UNIT-III
5. Explain a full adder circuit and subtractor circuit, with truth tasks. How they are used in parallel adders ?
6. Explain a decoder circuit. How code conversion is realized using ROM ? Explain.
7. What are the different triggering schemes used in flip flops ? Describe state reduction and state assignments. How sequential circuit are analyzed ?
8. Explain the design of a mod 10 and mod-12 counters and discuss their working.
UNIT - V
9. What are registers, ripple counters ? synchronous counters ? Design a shift left register and explain its working.
10. Write short notes on:
(a) Memory unit.
(b) Multi level gates and uses.
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Attachment: |
| Earning: Approval pending. |
