Birla Institute of Technology (BIT Mesra) 2004 MS Software Engineering Computer Organization

Birla Institute of Technology and Science, Pilani
Distance Learning Programmes Division
MS Software Engineering in Collaboration with Wipro Technologies
Second Semester 2003 – 2004
Comprehensive exam
Regular
Course No. : SEWP ZC413
Course Name : Computer Organization & Architecture
Nature of examination : Open book examination
weightage : 60 %
Duration : 3Hours
Date : July 17, 2004
Note: Attempt all ques.. begin every ans from a fresh page

1. For the control signal listing shown
PCout, MARin
MARout, MDRinm, learn
MDRout, IRin
R2out , R3out , Add, R1in
Write a micro program, design hard wired circuit and draw the timing diagram. (6)
2. Design a single precision and a double precision binary number for the provided decimal numbers (6)
A: 0.0001
B: 2345. 234

3. Design a 32 K RAM by using 4 8K RAMS. How many address lines are available to address RD, WR and chip choose. (6)

4. In the memory handling of a certain computer primary memory, secondary memory and cache are used. If the miss rate of cache is 0.10, miss penalty is 0.014 msecs and cache access time is 14 microsecs. compute the total access time in the fallowing cases.
a) data transfer is from secondary memory to primary memory and then to cache
b) data transfer is from primary memory to cache
The fallowing transfer rates are applicable.
Secondary memory to primary memory 0.2 msecs and primary memory to cache two microsecs transfer time ranging from primary memory and cache is negligible. (6)

5. Consider a cache with 128-word blocks .It takes 2 clock cycles to send an address to the main memory the 1st 2 words are accessed in a total time of 24 cycles. The following words are accessed in eight clock cycles per word. compute the total time needed for the entire info to be transferred into cache by assuming interleaved and non-interleaved memory. Hit rate of the cache = 91%
(6)

6 a). Consider a disc with 34 recording surfaces and 9000 tracks per surface, every track
has 500 sectors and every sector has 1024 bytes of data compute the latency and access time if seek time is 10 msecs.
b) In a 2 level memory ta1 = 0.02 secs and ta2 = 0.015 secs compute the miss rate
if the maximum access efficiency is 92 % (6)

7. Plot a characteristic of access efficiency and hit rate for r = four and r = 51, let the hit ratio vary from 0 to 1.
compute the avg. access time of a combination of 2 memories with costs of 0.01 and 0.2 respectively the access times being one micro sec and one milli sec respectively. Miss rate is 0.15. The capacities of the 2 memories are respectively 512 and one GB respectively. (6)

8 a) Calculate the conversion time of successive approximation ADC if the system
frequency is one pico hz, the chip is handling 16 bits for the provided data what is the maximum possible frequency if flash ADC is used.
b) Find the digital output of an ADC working in dual slope mode having t1 = 100
msecs, vf = 50 mv, vr = 48 mv the clock frequency being 15 Khz (6)

9. A16 bit ADC outputs all ones when input voltage is 6.2 v obtain resolution. obtain
digital output when input voltage is 1.87 v. obtain quantatising fault for the above chip at an analog voltage of nine v. (6)

10. Consider the generic program
ADD (R2), R1
MOV R1, R3
ADD R3, R4, R5
MOV R5, R6
compute the time of execution of the above segment if time of transfer ranging from memory and register is 0.3 m secs and time for arithmetic operation 0.1 micro secs .
(6)





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Earning:   Approval pending.