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Birla Institute of Technology (BIT Mesra) 2007 MS Software Engineering Digital Electronics

Saturday, 19 January 2013 03:40Web

Birla Institute of Technology and Science, Pilani
Distance Learning Programmes Division
MS Software Engineering in Collaboration with Wipro Technologies
Second Semester 2006 – 2007
Mid-semester exam
Regular
Course No. : SEWP ZC261
Course Name : Digital Electronics & Micro Processors
Nature of examination : Closed Book Bangalore
Weightage : 40 %
Duration : two Hours No of pages : 2
Date : March 18, 2007 (AN) No. of questions : 8

Note: Attempt all ques.. begin every ans from a fresh page

1.Given the subsequent truth table.
a)Express F1 in SOP & F2 in POS.
b)SimplifyF1 &F2 using K-map. (02+03)


x y z F1 F2
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

2. Simplify the switching function using Tabulation method.

F (W,X,Y,Z)= m ( 0,2,4,6,7,8,10 ) . where m= Min terms. (05)

3.a) Implement the decreased min terms using NAND gates only, for the function
F ( A,B,C,D )= m( 2,4,6,8,10, 12 ) +d c (3,5,7).wkere m= Min terms

b) Implement the decreased max terms using NOR gates only, for the function
F (W,X,Y,Z )= M (0,1,2,4,6,7,8,) +d c ( 10,12,14,15 ) where M= Max terms.
(2 ½ +2 ½ )
4. A majority circuit is acombinational circuit whose output is equal to one if the input variables have more 1’s than 0’s. The output is zero otherwise.. Deisgn a
3 –input majority circuit. ( 05 )


5. With the help of function table, Show the realization of full adder using 3:8 decder. (05)

6. a) Realize the subsequent switching function using 4:1 MUX.
F ( X,Y,Z )= m ( 1,2,5,7 ) (03 )

b) A 4 stage counter uses JK flip-flop with 10 micro seconds propagation delay.
compute the maximum frequency of operation of the counter oprating in
i) Asynchronous mode & ii) Synchronous mode. presume Tstrobe= 10 micro second. (02)

7. Design mod-6 synchronous counter using JK flip-flops. (05)

8. Realize ring counter and twisted ring counter using four bit shift register.
List the used and unused states in every case. Draw the timing diagrams in every case. (05)




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