Anna University Chennai 2005 B.Tech Information Technology Computer Architecture - Question Paper

CS 238-COMPUTER ARCHITECTURE-I

(Common to B.E.(Part-Time) 2nd Semester Regulation 2005)

Time:Three hours Maximum:100 marks


ans all ques.

(PART A-10*2=20 marks)
1.What is load store architecture?
2.Explain the absolute and auto increment addressing modes with an example instruction?
3.Discuss the IEEE format used for representing single-precision floating point numbers.
4.Discuss the principle of operation of a carry saver adder.
5.What are the advantages and disadvantages of hardwired and micro-programmed control?
6.What is the ideal speedup expected in a pipelined architecture with ‘n’ stages? Justify your ans.
7.Distinguish ranging from the write-through and write-back policies out their merits and demerits.
8.What is an interleaved memory system? explain.
9.Distinguish ranging from memory and mapped I/O and I/O mapped I/O.
10.Consider a computer in which several devices are to be serviced interrupts. How do you handle this if the processor has only 1 request line?

(PART B-5*16=80 marks)
11.(i).Consider the subsequent instruction
Add (R0)+R1,R2
Where the 1st 2 are source operands and the 3rd is the destination operand. Show the control sequence to execute this instruction for a single bus organization assuming the instruction itself is only a 1 word instruction [Marks-8]
(ii).What are the features to be considered while designing the instruction formats of a
processor? explain in detail. [Marks-8]

12.a).(i).Discuss the principle of operation of carry look ahead adder. [Marks-4]
(ii).Design a 64-bit adder that uses 4 16-bit carry-look ahead adders along with additional logic to generate c16,c32,c48 and c64 from c0 and the G1” and P1” variable. Also compute the delay for generating s63 and c64. [Marks-12]
(Or)
12.b).(i).Discuss the operation of floating point adder/subtractor unit. [Marks-12]
(ii).Simulate the addition operations on the operands:
A=0 10001 011011
B=1 01111 101010
With a five-bit signed excess-15 exponent and six-bit normalized fractionalized
Mantissa. [Marks-4]

13.a).Give the organization of a typical hardwired control unit and discuss the functions performed by the different blocks. explain the data flow for a simple instruction. [Marks-16]

(Or)

13.b).Discuss the different hazards that might arise in a pipeline. elaborate the remedies commonly adopted to overcome/minimize these hazards. [Marks-16]

14.a).(i).Discuss the different mapping techniques used in cache memories. [Marks-12]
(ii).A computer system has a main memory consisting of 1M words. It also has 8K word cache organized in the block-set-associative manner, with four blocks per set and 64 words per block. [Marks-4]
(Or)

14.b).(i).Explain the concept of virtual memory with any 1 virtual memory management techniques. [Marks-12]
(ii).Give the basic cell of an associative memory and discuss its operation. [Marks-4]

15.a).(i).What are the functions performed by a typical I/O interface? [Marks-4]
(ii).Explain the interrupt driven mode of data transfer and the DMA driven data transfer elaborating on how they are accomplished and their relative merits and demerits. [Marks-12]

(Or)
15.b).Write short notes on the subsequent
(i).Laser printers [Marks-8]
(ii).Any 2 input devices [Marks-8]

Earning:   Approval pending.