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Anna University Chennai 2007 B.Sc Computer Science OPERATING SYSTEMS - Question Paper

Friday, 01 March 2013 03:05Web

B. Sc. DEGREE exam

OPERATING SYSTEMS

Time : 3 Hours Maximum : 100 marks

ans ALL ques.

PART A – (10 X two = 20 marks)

1. What is meant by graceful degradation?
2. What is the situation that provide raise to Process Termination?
3. What is meant by a Thread? Mention its advantage.
4. Specify the significance of priority-inheritance protocol.
5. What are various methods of dealing deadlock problem?
6. What is Thrashing? How can it be prevented?
7. Enumerate the important attributes of a file.
8. What is meant by intenal and external fragmentation?
9. How linked allocation solves the issue of contiguous allocation?
10. What is the function of bootstrap loader?

PART B – (5 X 16 = 80 marks)

11. (a) (i) Write short notes on the subsequent terminologies : (8)

1. Time sharing systems
2. Distributed systems

(ii) What is the use of PCB? discuss the info specified in PCB. (8)

12. (a) explain in detail the various CPU scheduling algorithms with examples. (16)


(Or)

(b) (i) discuss the difference ranging from preemptive and non preemptive scheduling (8)
(ii) Suggest a solution that can solve critical part issue. (8)


13. (a) (i) explain in detail about the various methods available to recover from deadlock
after its detection. (8)

or

(b) (i) discuss the subsequent allocation algorithms : (16)
(i) First- Fit (ii) Best-Fit and
(iii) Worst-Fit

14. (a) (i) discuss the procedure used for handling a page fault. (8)
(ii) define any 2 page-replacement algorithm. (8)

(or)

(b) (i) Summarize the various kinds of file, their extension and the usage of every
File kind. (8)
(ii) define the most common schemes available for defining the logical structure
Of a directory. (8)

15. (a) explain in detail the subsequent 3 methods of allocating disk space.

(i) Contiguous allocation (ii) Linked allocation
(iii) Indexed allocation

(or)

(b) (i) Summarize the process of interrupt driven I/O cycle with a neat flow diagram. (8)

(ii) Briefly discuss the steps involved in Direct Memory Access data transfer. (8)







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