Anna University Chennai 2009-7th Sem B.E Electronics & Communication Engineering /B.Tech ,emr/emr . ester Electronics and Communication Engineering EC 1401-VLSI DESIGN - Question Paper

B.E/B.Tech Degree Examination,November/December 2009.
Seventh Semester
Electronics and Communication Engineering
EC 1401-VLSI DESIGN
(Common to B.E.(Part-Time) 6th Semester Regulation 2005)
(Regulation 2004)
Time:Three hours
Maximum:100 marks


ans all ques..
Part A-(10*2=20 marks)
1.What are the various MOS layers?
2.What are the 2 kinds of layout design rules?
3.Define rise time and fall time.
4.What is a pull down device?
5.What are the difference ranging from task and function?
6.What is the difference ranging from === and == ?
7.What is CBIC ?
8.Draw an assert high switch condition if input = 0 and input =1.
9.What do you mean by DFT?
10.Draw the boundary scan input logic diagram.

Part B - (5*16=80 marks)

11.a) explain the steps involved in IC fabrication process.(16)
Or
b) define n-well process in detail.(16)

12.a)i)Explain the DC characteristics of CMOS inverter with neat sketch.(8)
ii)Explain channel length modulation and body effect.(8)
Or
b)i)Explain the various regions of operation in a MOS transistor.(10)
ii)Write a note on MOS models.(6)

13.a)Explain in detail any 5 operators used in HDL .(16)
Or
b)i)Write the verilog code for four bit ripple carry full adder.(10)
ii)Give the structural description for priority encoder using verilog.(6)

14.a)Explain in detail the sequence of steps to design an ASIC.(16)
Or
b)Describe in detail the chip with programmable logic structures.(16)

15.a)Explain in detail Scan Based Test Techniques.(16)
Or
b)Discuss the 3 main design strategies for testability.(16)

Earning:   Approval pending.