Anna University Chennai 2011-6th Sem B.E Electronics & Communication Engineering VLSI / ( ECE) - Question Paper

B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2011.
Sixth Semester
Electronics and Communication Engineering
EC 2354 — VLSI DESIGN
(Regulation 2008)
(Common to PTEC 2354 – VLSI Design for B.E. (Part-Time) 5th Semester
Electronics and Communication Engineering, Regulation 2009)
Time : 3 hours Maximum : 100 marks
ans ALL ques..
PART A — (10 × two = 20 marks)
1. Determine whether an NMOS transistor with a threshold voltage of 0.7 V is operating in the saturation region if GS V = two V and =DS V 3V.
2. Write down the formula for describing the channel length modulation effect in NMOS transistors.
3. Write the expressions for the logical effort and parasitic delay of n input NOR gate.
4. Why does interconnect increase the circuit delay?
5. Draw a pseudo NMOS inverter.
6. elaborate the advantages of differential flip flops?
7. State the objective of functionality test.
8. elaborate the test fixtures needed to test a chip?
9. Write the Verilog module for an half adder.
10. elaborate the delay specifications available in Verilog HDL for modeling a
logic gate?
PART B — (5 × 16 = 80 marks)
11. (a) (i) An NMOS transistor has the subsequent parameters : gate oxide thickness = 10 nm, relative permittivity of gate oxide = 3.9, electron mobility = 520 two cm /V-sec, threshold voltage = 0.7 V, permittivity of free space = 14 10 85 . eight - × F/cm and (W/L) = 8. compute the drain current when ( GS V = two V and = DS V 1.2 V) and ( GS V = two V and = DS V two V) and also calculate the gate oxide capacitance per unit area. Note that W and L refer to the width and length of the channel respectively. (3 + three +
(ii) Draw and discuss the DC and transfer characteristics of a CMOS inverter with necessary conditions for the various regions of operation. (8)
Or
(b) (i) discuss the gate, source/drain formation and isolation steps of CMOS fabrication process with neat diagrams. (8)
(ii) provide a brief note on the various process techniques to enhance the performance of CMOS transistors. (8)

12. (a) (i) discuss the static and dynamic power dissipation in CMOS circuits with necessary diagrams and expressions. (10)
(ii) explain the principle of constant field scaling and also write its effect on device characteristics . (6)
Or
(b) (i) discuss the various reliability issues related to the design of reliable CMOS chips. (10)
(ii) provide a brief account on design margin. (6)




13. (a) (i) define the basic principle of operation of dynamic CMOS, domino and NP domino logic with neat diagrams (12)
(ii) Write the basic principle of low power logic design (4)
Or
(b) (i) Compare the sequencing in traditional domino and skew tolerant domino circuits with neat diagrams. (8)
(ii) discuss the issue of metastability with neat diagrams and expressions. (8)

14. (a) discuss the manufacturing test principles in detail. (16)
Or
(b) define the adhoc testing and scan based approaches to design for testability in detail. (16)

15. (a) (i) Draw the 3 input CMOS NOR and NAND gates and write the Verilog switch level modeling for both. (10)
(ii) discuss the continuous and implicit continuous assignment with 2 suitable examples for every. (6)
Or
(b) (i) Draw the logic diagram of four to one MUX using NAND gates and write the gate level modeling using Verilog HDL. (8)
(ii) provide a brief note on the looping statements available in Verilog HDL and write a verilog code for D Latch. (6 + 2)

Earning:   Approval pending.