Anna University Chennai 2005 B.E Electrical and Electronics Engineering Fifth Semester EE333 – Digital Systems - Question Paper

B.E. Electrical and Electronics Engineering
Fifth Semester
EE333 – Digital Systems
Time : three Hours Max Marks : 100
PART – A
ans All ques. (10 x two = 20 marks)
1. Why binary number system is used in digital system.
2. Represent the subsequent numbers in 2’s complement from
(i) +3 (ii) +25 (iii) –5 (iv) -11
3. find the subsequent operations using only NAND gates
(a) NOT (b) AND
4. describe the laws of Boolean Algebra.
5. Why TTL is preferred over DTL?
6. elaborate half and full adders?
7. describe the term triggering the flip flops
8. Distinguish the classification of sequential circuits.
9. describe Mask Programmable PLA and Field Programmable PLA.
10. provide the logic table of a ROM which will multiply 2 2-bit binary numbers.
PART - B
11.i) Specify the radix and the symbols used in (1) binary (2) ternary (3) quinary (4)
octal and (5) hexadecimal number system. (4)
ii) Convert (329.678)10 to an equivalent number in base six having a conversion fault
less than .001. (4)
iii) Design a parity generator to generate an odd parity bit for a 4-bit word. Use EXOR
and EX-NOR gates. (8)
12.a) Use Quine-Mccluskey method to find the minimal sum for the subsequent
function.
F(X1 X2 X3 X4) = S (0, 1, 3, 6, 7, 14, 15)
OR
12.b)i) Simplify the function using Karanaugh map. (8)
1) F(A, B, C, D) = S(0, 1, 2, 4, 5, 7, 11, 15)
2) F(W, X, Y,Z) = S(2, 3, 10, 11, 12, 13, 14, 15)
ii) Implement the subsequent function with either NAND or NOR gates. Use only 4
gates. Only the normal inputs are available. (1) d= wyz (2) F = w’ xz+w’
yz+x’+wx y’z. (8)
13.a)i) Construct a DTL NAND gate and discuss. (8)
ii) Design a combinational circuit that compares 2 4-bit numbers A and B to check
if they are equal or not. (8)
OR
13.b) Create the truth table for logic that receives BCD digit as input and provides 7
outputs to drive a seven segment display. Using the don’t cares, find the decreased
Boolean expression for the ‘b” and ‘e’ segments output of a seven segment display
driver.
14.a) A sequential circuit has 2 JK flip flops A and B, the inputs, X and Y and one
output, Z. The flip flop input function and the circuit output functions are as
follows.
JA = Bx + B’y’ KA = B’xy’
JB = A’x’ KB = A + xy’
1) Draw logic diagram (2) Tabulate the state table (3) Derive the next state
formula for A and B.
OR
14.b) List the PLA program table for the BCD to excess three code converter circuit and
show its implementation for any 2 output functions.
15.a) Analyze the circuit shown in Fig.1. find the state table and the state diagram
and determine the function of the circuit.
Fig. 1
OR
15.b)i) Implement the function
F(X1, X2, X3, X4) = S (0, 1, 3, 4, 8, 9, 15) with an eight x one multiplexer where the
subsequent variables are connected in the specified order to selection lines S2 S1
and S0 respectively.
1) X1, X2, X3 (2) X2, X3, X4 (8)
ii) define the working of a BCD ripple counter with neat circuit diagram. (8)
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Earning:   Approval pending.