Anna University Chennai 2011-6th Sem B.E Computer Science and Engineering Anna university in chennai for held on - exam paper

B.E/B.TECH DEGREE EXAMINATION,APRIL/MAY 2011
SIXTH SEMESTER
Computer science and engineering
CS 2354- ADVANCED COMPUTER ARCHITECTURE
(Regulation 2008)

Time: 3 hours maximum:100 marks

ans ALL ques.
PART A(2*10=20 marks)

1. what is loop unrolling? and elaborate its advantages?
2. differentiate ranging from static and dynamic branch predication approaches.
3. what is fine-grained multithreading and what is the advantage and disadvantages of fine -grained multithreading?
4. what a VLIW processor?
5. what is sequential consistency?
6. state the advantages of threading.
7. differentiate ranging from write-through cache and snoopy cache.
8. compare SDRAM with DRAM.
9. what is multi-core processor and elaborate the application areas of multi-core processors?
10.what is Cell Processor?

PART B(5*16=80 marks)

11. (a) Briefly define any techniques to decrease the cokntrol hazard stalls.(16)
or
(b) (i) explain about any 2 compiler techniques for exposing ILP in detail(8)
(ii) discuss how ILP is achieved using dynamic scheduling(8)

12. (a) (i) define the architectural features of IA64 Processors in detail(10)
(ii) discuss the architecture of a typical VLIW processor in detail(6)
or
(b)(i) define the architectural features of Itanium Processor(10)
(ii) discuss how instruction level parallelism is achieved in Epic processor(6)

13. (a) (i) define the basic structure of a centralized shared-memory multiprocessor in detail(6)
(ii) define the implementation of directory-based cache coherence protocol(10)
or
(b) (i) elaborate the advantages and disadvantages of distributed-memory multiprocessors? define the basic structure of a distributed memory multiprocessor in detail.(8)
(ii) define sequential and relaxed consistency model(6)

14. (a)(i) with suitable diagram, discuss how virtual address is mapped to L2 cache address.(10)
(ii) explain about the steps to be followed in designing I/O system(6)
or
(b) define the optimization techniques used in compiler to decrease cache miss rate(16)

15. (a)(i) define the feature of SUN CMP architecture in details(6)
(ii) elaborate multi core processors? discuss how a multi core processors works. (10)
or

(b) (i) explain aboyt the SMT kernel Structure in detail(8)
(ii) define the architecture of the IBM cell Processor in detail(8)

Earning:   Approval pending.