Anna University Chennai 2012-4th Sem B.E Computer Science and Engineering ./B.Tech , /E (ester, )-COMPUTER ORGANISATION AND ARCHITECTURE - Question Paper

B.E./B.Tech. DEGREE EXAMINATION, MAY/JUNE 2012
Fourth Semester
Computer Science and Engineering
CS 2253/141403/CS 43/CS1252 A/10144 CS 404/080250011-COMPUTER ORGANISATION AND ARCHITECTURE
(Common to info Technology)
(Regulation 2008)
Time : 3 hours
Maximum : 100 marks
ans all ques..
PART A-(10*2 = 20 MARKS)
1. What is SPEC? Specify the formula for SPEC rating.
2. What is relative addressing mode? When is it used?
3. Write the register transfer sequence for storing a word in memory.
4. What is hard-wired control? How is it various from micro-programmed control?
5. What is meant by data and control hazards in pipelining?
6. What is meant by speculative execution?
7. What is meant by an interleaved memory?
8. An address space is specified by 24 bits and the corresponding memory space by 16 bits:
How mmany words are in the
(a) virtual memory
(b) main memory
9. Specify the various I/O transfer mechanisms available.
10. What does isochronous data stream means?
PART B-(5*16 = 80 marks)
11. (a) (i) elaborate addresing modes? discuss the different addressing modes with examples. (8)
(ii) Derive and discuss an algorithm for adding and substracting two floating point binary numbers.(8)
Or
(b) (i) discuss instruction sequencing in detail. (10)
(ii) Differentiate Risc and Cisc architectures. (6)
12. (a) (i) With a neat diagram discuss the internal organisation of a processor. (6)
(ii) discuss how control signals are generated using microprogrammed control. (10)
Or
(b) (i) discuss the use of multiple-bus organisation for executing a three-operand instruction. (8)
(ii) discuss the design of hardwired control unit. (8)
13. (a) (i) Discus the basic concepts of pipelining. (8)
(ii) define the data path and control considerations for pipelining. (8)
Or
(b) define the techniques for handling data and instruction hazards in pipelining. (16)
14. (a) (i) discuss synchronous DRAM technology in detail. (8)
(ii) In a cache-based memory system using FIFO for cache page replacement, it is obtained that the cache hit ratio H is low.

The subsequent proposals are made for increasing.
(1) Increase the cache page size.
(2) Increase the cache storage capacity.
(3) Increase the main memory capacity.
(4) change the FIFO replacement policy by LRU.
Analyse every proposal to determine its probable impact on H. (8)
Or
(b) (i) discuss the varios mapping techniques associated with cache memories. (10)
(ii) discuss a method of translating virtual address to physical address. (6)
15. (a) discuss the following:
(i) Interrupt priority schemes. (8)
(ii) DMA. (8)
Or
(b) Write an elaborated note on PCI, SCSI and USB bus standards. (16)

Earning:   Approval pending.