Bharathidasan University 2009 M.Sc Information Technology Barathidasan University IT Computer Architecture - Question Paper

Barathidasan University
M.SC IT Computer Architecture
December 2009

part A — (10 x three = 30 marks)
ans ALL the ques..

1. State Amdal’s legal regulations and Principle of locality.
2. provide syntax for any 3 control flow instructions in MIPS.
3. discuss about the steps involved in instruction execution.
4. elaborate the different levels of Broach Prediction?
5. Write short notes about basic pipeline scheduling and loop unrolling.
6. List and discuss any 3 limitations of hardware versus software speculation mechanism.
7. How is a block obtained if it is in the Cache?
8. explain about bus design decisions.
9. What is multiprocessor Cache Coherence?
10. provide the basics about directory based Cache Coherence protocol.

part B — (4 x 10 = 40 marks)
ans any 4 ques..

11. discuss about the operands and operations of media and signal processing.
12. What is ILP? discuss its concepts and challenges.
13. define about basic VLIW approach.
14. Explain: INTEL IA – 64 Instruction Set Architecture.
15. explain about DRAM Technology.
16. discuss the basic models of memory consistency in detail.
part C — (2 ? 15 = 30 marks)
ans any 2 ques..
17. Write in brief about P6 micro architecture.
18. discuss how to expose more parallelism at compile time using hardware support.
19. With needed formulas discuss how to measure the performance of Cache?

Earning:   Approval pending.