Jawaharlal Nehru Technological University Kakinada 2009-2nd Sem B.Tech Code No: Q0402/R05 III Supplementary s, / VLSI DESIGN ( Common to Electronics & Communication Engineering, Bio-Medical En

Code No: Q0402/R05
III B.Tech II Semester Supplementary Examinations, Nov/Dec 2009
VLSI DESIGN
( Common to Electronics & Communication Engineering, Bio-Medical
Engineering and Electronics & Telematics)
Time: three hours
Max Marks: 80
ans any 5 ques.
All ques. carry equal marks

1. (a) explain the latest patterns in IC Technology.
(b) elaborate the advantages of ICs over discrete components?
(c) List the limitations of IC's.
[8+4+4]

2. (a) Derive the relation ship ranging from drain to source current Ids Verses Vds in non
saturated and saturated regions.
(b) Draw the graph of Ids Verses Vds for depletion and enhancement modes of a
MOS transistor.
[8+8]

3. Design a layout diagram for the CMOS logic shown beneath
Y = A + B + C .
[16]

4. (a) discuss clocked CMOS logic, domino logic and n-p CMOS logic.
(b) In gate logic, compare the geometry aspects ranging from 2 -input NMOS NAND
and CMOS NAND gates.
[8+8]

5. (a) discuss the CMOS system design based on the data path operators with a
suitable example.
(b) Draw and discuss the basic Memory- chip architecture. [8+8]

6. (a) Draw the typical standard-cell structure showing regular-power cell and ex-
plain it.
(b) Draw and discuss the pseudo-nMOS PLA schematic for full adder and what
are the advantages and disadvantages of it.
[8+8]

7. (a) What is the difference ranging from Flop-Flop and Latch? Write a VHDL program
for a latch.
(b) Why logic-level simulators are suitable for testing a fast and large CMOS
circuits and how to compute the delay of the gate?
[8+8]

8. (a) Why stuck-at faults occur in CMOS circuits? discuss with suitable logical
diagram and layout.
(b) Draw a schematic for a CMOS edge-sensitive scan-register and also draw a few
circuit level diagrams of its implementation.
[8+8]

Earning:   Approval pending.