Jawaharlal Nehru Technological University Hyderabad 2005-2nd Sem B.Tech Applied Electronics and Instrumentation III Supplementary s, ember/ember VLSI SYSTEMS DESIGN -university question paper

Code No: RR321202 Set No. 1
III B.Tech II Semester Supplementary Examinations,
November/December 2005
VLSI SYSTEMS DESIGN
(Information Technology)
Time: three hours Max Marks: 80
ans any 5 ques.
All ques. carry equal marks
? ? ? ? ?
1. Implement the subsequent gates with p-MOS transistors only and discuss its working
(a) three Input NAND gate.
(b) Inverter. [8+8]
2. An p-MOS transistor is operating in the triode region with the subsequent parameters
µnCox = 95 µ A/V two W/L ( ratio) = 90 Vgs = -4V, Vtn = -1.1V, Vds = -2V .
obtain its drain current & drain -Source resistance. [16]
3. discuss with neat sketches CMOS fabrication using P - well process. [16]
4. Design a layout for CMOS 2-input NOR gate. [16]
5. discuss with suitable example how to design the layout of a gate to maximize
performance and minimize area. [16]
6. Draw the structure of an un-signed array Multiplier and discuss its working. [16]
7. Clearly discuss about block placement and channel definition with respect to floor
planning of the chip. [16]
8. Write a register-transfer description of 1 four-digit timer.

Earning:   Approval pending.