Jawaharlal Nehru Technological University Hyderabad 2005-2nd Sem B.Tech Applied Electronics and Instrumentation III Supplementary s, ember/ember VLSI SYSTEMS DESIGN - university paper

Code No: RR321202 Set No. 2
III B.Tech II Semester Supplementary Examinations,
November/December 2005
VLSI SYSTEMS DESIGN
(Information Technology)
Time: three hours Max Marks: 80
ans any 5 ques.
All ques. carry equal marks
? ? ? ? ?
1. Implement the subsequent logic functions using CMOS logic
(a) Y = {(A + B)(C + D)}1
(b) Y = {AB + C}1 [8+8]
2. describe various current parameters of Digital IC and discuss their significance.[16]
3. discuss with neat sketches CMOS fabrication using twin - tub process. [16]
4. Design a layout for CMOS 2-input NAND gate. [16]
5. discuss clearly any 1 of the testing procedure to Test sequential Systems. [16]
6. Draw the circuit diagram of 4 transistor DRAM cell with storage nodes and
discuss its working. [16]
7. Clearly discuss about block placement and channel definition with respect to floor
planning of the chip. [16]
8. discuss about design methodology for 1BM ASICS.

Earning:   Approval pending.