Jawaharlal Nehru Technological University Hyderabad 2005-2nd Sem B.Tech Applied Electronics and Instrumentation III Supplementary s, ember/ember VLSI SYSTEMS DESIGN - exam paper

Code No: RR321202 Set No. 3
III B.Tech II Semester Supplementary Examinations,
November/December 2005
VLSI SYSTEMS DESIGN
(Information Technology)
Time: three hours Max Marks: 80
ans any 5 ques.
All ques. carry equal marks
? ? ? ? ?
1. Implement the subsequent gates with p-MOS transistors only and discuss its working
(a) two Input AND gate.
(b) four Input NOR gate. [8+8]
2. Name various IC fabrication technologies with suitable examples. [16]
3. Design a stick diagram for two-input N-MOS NAND and NOR gates. [16]
4. discuss about domino-logic and draw the transistor schematic of a two-input AND
gate in domino logic. [16]
5. discuss the details of standard cell layout design method. [16]
6. Draw the circuit diagram of resistive load SRAM cell and discuss its working prin-
ciple. [16]
7. discuss clearly the global routing phase of the floor planning of the chip with few
examples by considering all constraints. [16]
8. Design a block diagram for a PDP-8 data path that supports both one-bit and
two-bit rotations.

Earning:   Approval pending.