Jawaharlal Nehru Technological University Hyderabad 2005-2nd Sem B.Tech Applied Electronics and Instrumentation III Supplementary s, ember/ember VLSI SYSTEMS DESIGN - Question Paper

Code No: RR321202 Set No. 4
III B.Tech II Semester Supplementary Examinations,
November/December 2005
VLSI SYSTEMS DESIGN
(Information Technology)
Time: three hours Max Marks: 80
ans any 5 ques.
All ques. carry equal marks
? ? ? ? ?
1. Implement the subsequent gates with CMOS Logic and discuss its working
(a) Ex-OR gate.
(b) two Input NOR gate. [8+8]
2. (a) describe the terms SSI, MSI, LSI and VLSI.
(b) describe the terms fan-out, fan-in, Propagation delay and noise margin of a
logic-family. [8+8]
3. What is a stick diagram and discuss about various symbols used for components
in stick diagram. [16]
4. Design a layout for CMOS three - input OR gate. [16]
5. discuss in detail the path - delay measurement of the combinational logic circuits.
[16]
6. Draw the structure of carry choose adder and discuss its working principle. [16]
7. discuss clearly block placement phase of the Floor planning of the chip with suit-
able examples. [16]
8. Draw the state transition graph for the kitchen timer chip’s controller.

Earning:   Approval pending.